RTL Verification Engineer - Pre-Silicon (Hybrid)

Intel Corporation; Folsom (CA); Hybrid; USD 106,000 - 200,000; Full time

Benefits offered by this job

Stock bonuses

Health insurance

Retirement plan

Vacation

Job summary

Intel Corporation in Hillsboro/US hybrid location is seeking an Experienced Verification Engineer to design and develop UVM-based testbenches for complex digital systems. You will own verification strategies, integrate RTL components into SoCs, and drive power and SVA-based validation across multiple projects.

You’ll collaborate with architecture, physical design, and post-silicon teams, applying post-silicon learnings to enhance pre-silicon methodologies and deliver robust silicon solutions.

Qualifications

• Experience with pre-silicon logic validation using SystemVerilog and UVM.
• Experience in Digital design using Verilog and/or SystemVerilog.
• Experience with pre-silicon validation closure across multiple projects.
• Hands-on experience with UVM testbench design, focusing on reusability and scalability.
• Experience with end-to-end validation strategies for complex digital systems.
• Experience with SystemVerilog Assertions (SVA) for coverage closure.
• Experience with coverage-driven verification methodologies.
• Scripting proficiency in Python, Perl, or TCL for automation.

Responsibilities

• Design & Develop Verification Environments – Build and maintain UVM-based testbenches and test cases for mixed-signal CMOS designs.
• Define Verification Strategy – Own verification plans ensuring coverage closure across projects.
• RTL Development & Integration – Develop RTL designs and integrate logic into SoC architectures with IP providers.
• Power Methodology – Develop power verification methodologies for mixed-signal IPs.
• Assertion-Based Verification – Create and apply SystemVerilog Assertions for coverage closure.
• Debug & Root Cause Analysis – Identify and resolve pre-silicon failures and drive issues to closure.
• Cross-Team Collaboration – Work with architecture, physical design, and post-silicon teams.
• Continuous Improvement – Incorporate post-silicon learnings into pre-silicon methodologies.
• Documentation & Reviews – Maintain test plans and lead technical reviews.

Skills

SystemVerilog

UVM

Verilog

SVA

Python

Debugging

Analytical thinking

Documentation

Education

Master’s degree in Electrical/Computer Engineering or STEM field

Bachelor’s degree in Electrical/Computer Engineering or STEM field

Tools

UPF

Job description

Intel Corporation in Hillsboro/US hybrid location is seeking an Experienced Verification Engineer to design and develop UVM-based testbenches for complex digital systems. You will own verification strategies, integrate RTL components into SoCs, and drive power and SVA-based validation across multiple projects.

You’ll collaborate with architecture, physical design, and post-silicon teams, applying post-silicon learnings to enhance pre-silicon methodologies and deliver robust silicon solutions.