Principal Design Verification Architect (SystemVerilog/UVM)

Renesas Electronics Corp.; California (MO); On-site; USD 140,000 - 210,000; Full time

Job summary

Renesas Electronics seeks a Principal Design Verification Engineer to lead verification strategy for next‑generation semiconductor memory interface products, including data buffer silicon.

The role emphasizes deep SystemVerilog and UVM expertise, ownership of verification at block and system levels, and collaboration with RTL/design teams to meet functional and performance requirements. Preference for DDR4/DDR5 familiarity and future DDR6 exposure is noted.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Extensive experience in semiconductor design verification with ownership of complex verification efforts.
• Expert-level proficiency with SystemVerilog.
• Significant hands-on experience with UVM (Universal Verification Methodology) including development and optimisation of UVM-based verification environments.
• Experience defining verification strategies and developing verification plans from design and product specifications.
• Strong experience with functional verification, constrained-random testing, functional coverage, checkers, debugging, and coverage closure.
• Experience partnering with RTL/design engineering teams throughout the verification lifecycle.
• Demonstrated ability to independently solve complex verification and design problems.
• Ability to provide technical leadership and mentoring within a verification team.

Responsibilities

• Lead verification strategy and execution for complex semiconductor designs at the block and system level.
• Define verification methodologies, test plans, coverage strategies, and verification environments.
• Architect, develop, maintain, and optimize SystemVerilog/UVM testbenches and verification environments.
• Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure.
• Take technical ownership of verification for assigned blocks, features, and environments from planning through signoff.
• Work closely with RTL and design engineers to ensure designs meet functional and performance requirements and are effectively verifiable.
• Analyze specifications, design implementation, and verification results to identify functional gaps and design issues.
• Drive debugging and resolution of complex verification failures.
• Develop scalable and reusable verification components, methodologies, and best practices.
• Identify and lead improvements in verification efficiency, quality, performance, and reuse.
• Participate in architecture, feasibility, design, and technical reviews.
• Provide technical guidance and mentorship to verification engineers.
• Serve as a technical expert for assigned verification methodologies and tools.
• Communicate verification progress, coverage, technical risks, and readiness to engineering leadership and project stakeholders.

Skills

SystemVerilog

UVM

Semiconductor design verification

Technical leadership

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

SystemVerilog/UVM testbenches

Job description

Renesas Electronics seeks a Principal Design Verification Engineer to lead verification strategy for next‑generation semiconductor memory interface products, including data buffer silicon.

The role emphasizes deep SystemVerilog and UVM expertise, ownership of verification at block and system levels, and collaboration with RTL/design teams to meet functional and performance requirements. Preference for DDR4/DDR5 familiarity and future DDR6 exposure is noted.