Lead Digital Verification Architect – DDR5/DDR6

Renesas Electronics Corp.; Chandler (AZ); On-site; USD 140,000 - 190,000; Full time

Job summary

Renesas Electronics Corp. is seeking a senior verification engineer to drive the memory interface data buffer verification for DDR5/DDR6 and beyond.

You will be responsible for developing and executing verification plans, test benches, and coverage metrics in collaboration with a team of engineers. The role emphasizes SystemVerilog/UVM-based verification, reusable test environments, and close collaboration with the design team to ensure testability and high-quality results in datacenter-grade

Qualifications

• Masters in Electrical Engineering, or equivalent, with 8+ years of experience.
• Bachelor's Degree in Electrical/Computer Engineering or equivalent with 10+ years of experience.

Responsibilities

• Verify DDR5 Data Buffer to meet functional and performance specs.
• Integrate and test on System-level and block-level using UVM methodology.
• Develop verification plans based on specifications and contribute to test coverage.
• Drive verification strategy, plans, coverage, and execute tests with expert guidance.

Skills

UVM methodology

SystemVerilog

Verification

Testbench development

Memory interface

Education

Masters in Electrical Engineering

Bachelor's in Electrical Engineering

Tools

Verilog simulators

DDR5/DDR6 familiarity

Job description

Renesas Electronics Corp. is seeking a senior verification engineer to drive the memory interface data buffer verification for DDR5/DDR6 and beyond.

You will be responsible for developing and executing verification plans, test benches, and coverage metrics in collaboration with a team of engineers. The role emphasizes SystemVerilog/UVM-based verification, reusable test environments, and close collaboration with the design team to ensure testability and high-quality results in datacenter-grade