Lead Software Engineer - Low-Power Verification (UPF)

Cadence Design Systems; San Jose (CA); On-site; USD 115,000 - 213,000; Full time

Job summary

Cadence Design Systems in California is seeking a Lead Software Engineer - Low Power Verification to advance UPF debug features and RTL support as part of Palladium and Protium flows.

You will enhance UPF performance, scale event logging for multi-billion-gate designs, and help document end-to-end workflows with SystemVerilog and UPF examples. Collaboration across R&D, PE and AE teams is required, with a focus on high-quality, scalable software.

Qualifications

• Bachelor's degree in CS, EE, or related field; MS/PhD with experience acceptable.
• Strong knowledge of IEEE 1801 UPF and RTL languages (Verilog/SystemVerilog/VHDL).
• Proficient in debugging and reading C++ code; able to reason about designs.

Responsibilities

• Enhance UPF debug features across PPC and MC workflows; Dielet UPF support.
• Scale UPF event logging and violation detection for multi-billion-gate designs.
• Rebuild UPF documentation around end-to-end workflows with SystemVerilog and UPF examples.
• Help develop AI-assisted UPF debug tools to reduce time-to-root-cause.
• Collaborate with R&D, PE and AE to deploy UPF solutions across flows; unify UPF across Palladium and Protium.

Skills

C++ code reading

Debugging

AI coding tools

Communication skills

Education

BS in CS/EE or related

MS with 2+ years

PhD with 1+ year

Tools

IEEE 1801 UPF

Verilog

SystemVerilog

VHDL

Job description

Cadence Design Systems in California is seeking a Lead Software Engineer - Low Power Verification to advance UPF debug features and RTL support as part of Palladium and Protium flows.

You will enhance UPF performance, scale event logging for multi-billion-gate designs, and help document end-to-end workflows with SystemVerilog and UPF examples. Collaboration across R&D, PE and AE teams is required, with a focus on high-quality, scalable software.