Lead Design Engineer - RTL & IC Verification

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Cutting-edge technology

One Cadence – One Team

Career development

Job summary

Cadence Design Systems, Inc. in San Jose is seeking an experienced verification engineer to implement and verify Palladium and Protium based SOC validation, focusing on timing closure and readiness for tape-out.

You will work within Cadence's world-class toolchain to ensure design integrity and performance across advanced nodes. Collaborating with Front End RTL and Back End Verification teams, you will perform RTL synthesis, clock-tree construction, and timing analysis using Cadence tools.

Qualifications

• BS in Electrical Engineering with 5+ years experience or MS with 3+ years.
• Experience with Cadence tools: Innovus, Tempus, QRC, Voltus, Pegasus.
• Experience with 5nm, 3nm and 2nm nodes.
• Proficiency with Linux scripting: Shell, Perl, TCL, Python.
• Knowledge of PCI Express, DDR, LPDDR, SRAM, UCIe interfaces.

Responsibilities

• RTL synthesis and floorplanning.
• Build clock trees and optimizations.
• Close timing, IR drop and physical verification.
• Review and document designs for taping out.
• Interface with Front End RTL and Back End Verification teams.

Skills

Cadence tools experience (Innovus, Tem

RTL/SoC verification

Linux scripting (Shell, Perl, TCL, Py)

Digital design concepts

High-speed interfaces knowledge (PCIe,

Education

BS in Electrical Engineering

MS in Electrical Engineering

Tools

Innovus

Tempus

QRC

Voltus

Pegasus

Linux

Shell scripting

Job description

Cadence Design Systems, Inc. in San Jose is seeking an experienced verification engineer to implement and verify Palladium and Protium based SOC validation, focusing on timing closure and readiness for tape-out.

You will work within Cadence's world-class toolchain to ensure design integrity and performance across advanced nodes. Collaborating with Front End RTL and Back End Verification teams, you will perform RTL synthesis, clock-tree construction, and timing analysis using Cadence tools.