Lead Software Engineer - Low-Power Verification

Cadence Design Systems; San Jose (CA); On-site; USD 115,000 - 213,000; Full time

Benefits offered by this job

Paid vacation

Paid holidays

401(k) plan with employer match

Employee stock purchase plan

Medical, dental, and vision

Job summary

Cadence Design Systems in San Jose is seeking a Lead Software Engineer to advance low-power verification software for Palladium and Protium platforms. You will improve UPF compilation performance, add support for new IEEE 1801 LRM revisions, and document end-to-end workflows with SystemVerilog and UPF examples.

You will work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, Dielets) and ensure code and docs stay in sync through example-driven checks.

Qualifications

• Experience with UPF and RTL languages is required.
• Strong knowledge of Verilog/SystemVerilog and VHDL is expected.
• Proven ability to read and reason about C++ code and OO designs.

Responsibilities

• Contribute to the UPF compilation flow and improve performance.
• Rebuild UPF documentation with end-to-end workflows and examples.
• Collaborate with R&D, PE and AE teams to deploy UPF solutions across flows.

Skills

UPF knowledge

Verilog

SystemVerilog

VHDL

C++

Python

Perl

Tcl/Tk

AI coding tools

Technical writing

Education

BS in CS/EE

MS in CS/EE

PhD (related)

Tools

Copilot

Claude

Cursor

Job description

## Lead Software Engineer - Low-Power VerificationApply: SAN JOSE: Full time: Posted Today: End Date: December 31, 2026 (30+ days left to apply): R56209## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**Join our team and help build the next generation of low-power verification software for the Palladium and Protium emulation and prototyping platforms. As a Lead Software Engineer on the Palladium and Protium UPF R&D team you will be responsible for improving UPF compilation performance and correctness, adding support for new IEEE 1801 LRM revisions, and rebuilding UPF documentation around end-to-end workflows for multi-billion-gate low-power designs.What you will do* Contribute to the UPF compilation flow -- improve compilation performance, reduce instrumented capacity, and add self-checks across Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.* Rebuild UPF documentation around end-to-end compilation workflows, backed by valid SystemVerilog and UPF examples, and keep code and docs in sync through example-driven checks.* Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets -- each with UPF in 2- and 4-state).* Help consolidate and unify UPF compilation across Palladium and Protium.What we are looking for* BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience.* Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).* Ability to read, review, and reason about C++ code and object-oriented designs.* Scripting experience in Perl, Tcl/Tk, and/or Python.* Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output.* Strong technical writing skills — able to author user guides, specifications, and workflow-first documentation.*The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.*