Lead Software Engineer: Low-Power Verification (Equity)

Cadence Design Systems; San Jose (CA); Hybrid; USD 115,000 - 213,000; Full time

Benefits offered by this job

Paid vacation

Paid holidays

401(k) plan with employer match

Employee stock purchase plan

Medical, dental, and vision

Job summary

Cadence Design Systems in San Jose is seeking a Lead Software Engineer to advance low-power verification software for Palladium and Protium platforms. You will improve UPF compilation performance, add support for new IEEE 1801 LRM revisions, and document end-to-end workflows with SystemVerilog and UPF examples.

You will work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, Dielets) and ensure code and docs stay in sync through example-driven checks.

Qualifications

• Experience with UPF and RTL languages is required.
• Strong knowledge of Verilog/SystemVerilog and VHDL is expected.
• Proven ability to read and reason about C++ code and OO designs.

Responsibilities

• Contribute to the UPF compilation flow and improve performance.
• Rebuild UPF documentation with end-to-end workflows and examples.
• Collaborate with R&D, PE and AE teams to deploy UPF solutions across flows.

Skills

UPF knowledge

Verilog

SystemVerilog

VHDL

C++

Python

Perl

Tcl/Tk

AI coding tools

Technical writing

Education

BS in CS/EE

MS in CS/EE

PhD (related)

Tools

Copilot

Claude

Cursor

Job description

Cadence Design Systems in San Jose is seeking a Lead Software Engineer to advance low-power verification software for Palladium and Protium platforms. You will improve UPF compilation performance, add support for new IEEE 1801 LRM revisions, and document end-to-end workflows with SystemVerilog and UPF examples.

You will work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, Dielets) and ensure code and docs stay in sync through example-driven checks.