Lead Software Engineer - Low Power Verification

Cadence Design Systems; San Jose (CA); On-site; USD 115,000 - 213,000; Full time

Job summary

Cadence Design Systems in California is seeking a Lead Software Engineer - Low Power Verification to advance UPF debug features and RTL support as part of Palladium and Protium flows.

You will enhance UPF performance, scale event logging for multi-billion-gate designs, and help document end-to-end workflows with SystemVerilog and UPF examples. Collaboration across R&D, PE and AE teams is required, with a focus on high-quality, scalable software.

Qualifications

• Bachelor's degree in CS, EE, or related field; MS/PhD with experience acceptable.
• Strong knowledge of IEEE 1801 UPF and RTL languages (Verilog/SystemVerilog/VHDL).
• Proficient in debugging and reading C++ code; able to reason about designs.

Responsibilities

• Enhance UPF debug features across PPC and MC workflows; Dielet UPF support.
• Scale UPF event logging and violation detection for multi-billion-gate designs.
• Rebuild UPF documentation around end-to-end workflows with SystemVerilog and UPF examples.
• Help develop AI-assisted UPF debug tools to reduce time-to-root-cause.
• Collaborate with R&D, PE and AE to deploy UPF solutions across flows; unify UPF across Palladium and Protium.

Skills

C++ code reading

Debugging

AI coding tools

Communication skills

Education

BS in CS/EE or related

MS with 2+ years

PhD with 1+ year

Tools

IEEE 1801 UPF

Verilog

SystemVerilog

VHDL

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our team and help build the next generation of low-power verification software for the Palladium and Protium emulation and prototyping platforms.

As a Lead Software Engineer - Low Power Verification you will be responsible for improving the performance and usability of UPF debug features, adding support for new IEEE 1801 LRM revisions, and rebuilding UPF documentation around end-to-end workflows for multi-billion-gate low-power designs.

What you will do:

• Enhance UPF debug features -- improve performance and usability across the Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.
• Scale UPF event logging and violation detection – apply new techniques to capture and report more UPF events, with better multi-billion-gate low-power designs.
• Rebuild UPF documentation around end-to-end debug scenarios and workflows, backed by valid SystemVerilog and UPF examples.
• Help develop AI-assisted UPF debug tools to reduce time-to-root-cause for low-power design issues.
• Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets -- each with UPF in 2- and 4-state).
• Help consolidate and unify UPF debug across Palladium and Protium.

What we are looking for

• BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience.
• Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
• Strong debugging skills — root-cause analysis from logs, waveforms, traces, testcases, and user reports.
• Ability to read, review, and reason about C++ code and object-oriented designs.
• Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output.
• Strong communication and technical writing skills — able to turn scattered debug evidence into clear, user-facing workflows.

The annual salary range for California is $114,800 to $213,200.

You may also be eligible to receive incentive compensation: bonus, equity, and benefits.

Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.

Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Our benefits programs include:

• paid vacation and paid holidays
• 401(k) plan with employer match
• employee stock purchase plan
• a variety of medical, dental and vision plan options
• and more

We’re doing work that matters. Help us solve what others can’t.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.