Sr Principal Design Engineer – Palladium/Protium Enablement

Cadence Design Systems; San Jose (CA); On-site; USD 154,000 - 286,000; Full time

Benefits offered by this job

Paid vacation

401(k) plan with employer match

Employee stock purchase plan

Medical, dental and vision plans

Job summary

Cadence Design Systems in California invites experienced engineers to join our North America Palladium and Protium HW Development team. You will work directly with leading semiconductor customers to deploy Cadence's hardware emulation and FPGA prototyping platforms, developing and delivering high‑impact verification solutions.

In this highly visible, customer‑facing role, you will bridge hardware and software teams, define customer requirements, drive advanced protocol validation (PCIe, CXL) and

Qualifications

• Strong fundamentals in digital design, computer architecture, and system‑level verification.
• Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C++.
• Knowledge of high‑speed interfaces and memory protocols (e.g., PCIe, CXL).
• Debugging with waveforms, logs, and protocol analyzers.
• Ability to bridge hardware and software disciplines across teams.

Responsibilities

• Collaborate with frontline engineering teams and customers to develop, deploy, productize, and optimize advanced protocol solutions on Palladium and Protium platforms.
• Define and develop customer-specific emulation and prototyping requirements, focusing on leading edge high-speed interfaces and memory protocols.
• Drive the development of advanced acceleration FW + FPGA system solutions, establish robust verification methodologies, and support Cadence emulation tools.
• Triage and resolve complex, systemic issues across the hardware/software boundary, optimizing driver behavior, protocol compliance, and overall system stability.
• Lead technical evaluations and develop high-performance benchmarks to demonstrate the competitive advantages of Cadence hardware platforms.
• Create and deliver impactful technical presentations, white papers, and product demonstrations for existing and prospective customers.

Skills

Digital design fundamentals

SystemVerilog/Verilog

C/C++

Computer architecture

System-level verification

Emulation/FPGA prototyping

Interconnect protocols

Debugging with waveforms/logs

Cross-functional collaboration

Excellent communication

Job description

Cadence Design Systems in California invites experienced engineers to join our North America Palladium and Protium HW Development team. You will work directly with leading semiconductor customers to deploy Cadence's hardware emulation and FPGA prototyping platforms, developing and delivering high‑impact verification solutions.

In this highly visible, customer‑facing role, you will bridge hardware and software teams, define customer requirements, drive advanced protocol validation (PCIe, CXL) and