Senior Power Analysis Engineer - Signoff & Flow Optimization

Cadence; San Jose (CA); On-site; USD 115,000 - 213,000; Full time

Job summary

Cadence in California is seeking a skilled engineer to join our Power Analysis team, focusing on developing, debugging, and deploying Signoff power analysis flows at customer environments. You will closely work with R&D to integrate with synthesis and PnR stages and provide hands-on customer support.

The role requires hands-on Signoff power analysis experience, UPF knowledge, Verilog/SystemVerilog, and scripting skills; you will help optimize power, automate flows, document findings, and

Qualifications

• Hands-on experience with Signoff power analysis (static and dynamic power).
• Knowledge of power optimization techniques in Synthesis (clock gating, operand isolation, multi-Vt cell selection).
• Working knowledge of UPF (Unified Power Format) — power domains, isolation, level shifting, retention.
• Proficiency in Verilog/SystemVerilog for design analysis and testcase creation.
• Understanding of digital design fundamentals — clock domains, pipeline stages, timing/power trade-offs.
• Experience with low-power design methodologies (DVFS, power gating, multi-voltage).
• Familiarity with Liberty (.lib) and SPEF formats.
• Scripting skills: Tcl, Python, or Shell.
• Familiarity with tools such as Joules, Voltus, PTPX or equivalent.

Responsibilities

• Closely work with R&D to develop and maintain Signoff power analysis flows including integration with synthesis and PnR stages.
• Reproduce, debug, and resolve customer-reported issues in power analysis tools and flows.
• Deploy and validate power analysis tools at customer sites; provide hands-on technical support.
• Collaborate with customers to optimize power results and flow efficiency.
• Contribute to flow automation and scripting for repeatable deployments.
• Document debug findings, best practices, and flow guidelines.

Skills

Power analysis

Clock gating

Operand isolation

Multi-Vt cell

UPF

Verilog/SystemVerilog

Digital design

DVFS

Power gating

Multi-voltage

Liberty

SPEF

Tcl

Python

Shell

Joules

Voltus

PTPX

Education

Electronics / VLSI

Tools

Joules

Voltus

PTPX

Job description

Cadence in California is seeking a skilled engineer to join our Power Analysis team, focusing on developing, debugging, and deploying Signoff power analysis flows at customer environments. You will closely work with R&D to integrate with synthesis and PnR stages and provide hands-on customer support.

The role requires hands-on Signoff power analysis experience, UPF knowledge, Verilog/SystemVerilog, and scripting skills; you will help optimize power, automate flows, document findings, and