Lead SoC Physical Design Architect

Efficient Computer; Austin (TX); On-site; USD 200,000 - 250,000; Full time

Benefits offered by this job

Equity program

401K match

Paid parental leave

Flexible benefits

Job summary

Efficient Computer is seeking a Lead Physical Design Engineer to own the SOC top from block integration through timing, power, signal integrity, and tapeout-ready GDS. This hands-on role requires coordinating with DFT, package/IO, and architecture teams while delivering convergence across a complex design in a fast-moving, small team.

You will lead full-chip timing closure across corners, optimize PDN, manage power and signal integrity, and drive tapeout readiness with sign-off checklists.

Qualifications

• 5+ years of experience in physical design with full-chip ownership.
• 8-12+ years PD experience with multiple tapeouts.
• Hands-on with advanced nodes and timing closure.
• Experience with DFT, packaging, and analog/mixed-signal integration.
• Excellent scripting in TCL and Python; strong leadership skills.

Responsibilities

• Own full-chip timing closure across corners and modes.
• Lead power planning, IR drop analysis, and PDN design.
• Coordinate DFT, package IO, and architecture for convergence.
• Oversee physical verification and tapeout readiness.
• Mentor PD engineers and set flow standards.
• Drive cross-team decisions and schedule risk mitigation.

Skills

Strong leadership

Cross-team coordination

Scripting in TCL

Python scripting

Education

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Innovus

ICC2

Tempus/PrimeTime

RedHawk

Calibre

Job description

Efficient Computer is seeking a Lead Physical Design Engineer to own the SOC top from block integration through timing, power, signal integrity, and tapeout-ready GDS. This hands-on role requires coordinating with DFT, package/IO, and architecture teams while delivering convergence across a complex design in a fast-moving, small team.

You will lead full-chip timing closure across corners, optimize PDN, manage power and signal integrity, and drive tapeout readiness with sign-off checklists.