HBM SoC DFT Engineer — Testability & Bring-Up Lead

Micron Technology, Inc.; Folsom (CA); On-site; USD 146,000 - 247,000; Full time

Job summary

Micron Technology, Inc. is seeking an experienced DFT Engineer to own SoC‑level test architectures for high‑bandwidth memory (HBM) SoCs.

You will drive DFT definitions early in the design cycle, align with RTL, physical design, and integration teams, and ensure testability across pre‑ and post‑silicon stages. You will collaborate with CAD, verification, and manufacturing teams to optimize DFT implementations for complex dies, mentor engineers, and contribute to next‑gen HBM generations.

Qualifications

• Strong hands‑on experience with SoC develop for test (DFT) architecture and implementation, including scan, MBIST/LBIST concepts, boundary scan (JTAG), and ATPG.
• Experience working across full RTL‑to‑GDS SoC flows and collaborating with synthesis, STA, and physical design teams.
• Proficiency using industry‑standard EDA tools for DFT and implementation.
• Bachelor’s degree in Electrical or Computer Engineering, or equivalent practical experience.
• Seven or more years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs/SoCs.

Responsibilities

• Own SoC‑level DFT structures and their implementation across base‑die builds.
• Define and drive DFT architecture early in the design cycle with alignment to SoC integration and physical constraints.
• Implement and integrate DFT logic at block, subsystem, and full‑chip levels with RTL/SoC teams.
• Complete and sign off DFT flows, including ATPG readiness and coverage closure.
• Collaborate with physical design teams to optimize DFT for placement, routing, and LVS/DRC signoff.
• Coordinate with verification, test, and manufacturing teams to ensure testability and pre/post‑silicon readiness.
• Mentor engineers and drive innovation for future HBM generations.

Skills

SoC DFT architecture

MBIST/LBIST

ATPG

JTAG boundary scan

RTL‑to‑GDS flows

EDA tools (Siemens, Synopsys, Cadence)

Scripting (Python, Tcl, Perl)

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Tools

Siemens EDA

Synopsys

Cadence

Job description

Micron Technology, Inc. is seeking an experienced DFT Engineer to own SoC‑level test architectures for high‑bandwidth memory (HBM) SoCs.

You will drive DFT definitions early in the design cycle, align with RTL, physical design, and integration teams, and ensure testability across pre‑ and post‑silicon stages. You will collaborate with CAD, verification, and manufacturing teams to optimize DFT implementations for complex dies, mentor engineers, and contribute to next‑gen HBM generations.