Lead Silicon Architect for AI XPU: Tapeout to Bring-Up

Clera; San Francisco (CA); On-site; USD 200,000 - 300,000; Full time

Benefits offered by this job

Visa sponsorship available

Job summary

Clera is a well-funded AI accelerator startup seeking a founding silicon team member to lead the full journey of a custom XPU—from FPGA prototype through tapeout and bring‑up. You will set technical direction across architecture, RTL, verification, and tooling as the silicon organization grows.

Responsibilities include leading FPGA prototype development, guiding RTL for the first ASIC, and building comprehensive flows for rapid iteration and tapeout readiness. Visa sponsorship available.

Qualifications

• 8+ years hands-on digital design or silicon engineering experience (RTL, FPGA, or ASICs).
• Proven ability to ship SystemVerilog/Verilog in production silicon or FPGA.”
• End-to-end FPGA experience: RTL through place-and-route to hardware.
• Strong fundamentals in pipelines, clocks, resets, latency, throughput.
• Fluency with simulation, linting, synthesis, timing, and CDC verification flows.
• Experience automating hardware flows using Python, Tcl, Make, or similar.
• Background in AI accelerators or low-level AI kernel work.
• Tapeout, high-speed interface design, formal verification, UVM, cocotb, firmware or systems programming is a bonus.

Responsibilities

• Lead FPGA prototype development and optimize the XPU from spec to working silicon.
• Design and review RTL for the first ASIC, ensuring clean microarchitecture and synthesizable code.
• Build lint, simulation, synthesis, timing, and verification flows for rapid iteration and tapeout readiness.
• Make architecture decisions across compute datapaths, memory, interconnect, and control logic.
• Drive tapeout, bring-up, and delivery milestones, including critical sprints.
• Grow and mentor the silicon team as the company scales.

Tools

SystemVerilog

Verilog

RTL design

FPGA prototyping

ASIC development

Python scripting

Tcl

Make

Nix

UVM

Cocotb

Formal verification

CDC verification

Synthesis

Timing closure

Linting

SDC constraints

Tapeout

High-speed interfaces

Firmware

Systems programming

Job description

Clera is a well-funded AI accelerator startup seeking a founding silicon team member to lead the full journey of a custom XPU—from FPGA prototype through tapeout and bring‑up. You will set technical direction across architecture, RTL, verification, and tooling as the silicon organization grows.

Responsibilities include leading FPGA prototype development, guiding RTL for the first ASIC, and building comprehensive flows for rapid iteration and tapeout readiness. Visa sponsorship available.