AI Silicon Architect: RTL & Microarchitecture for Tape-out

Acceler8 Talent; Mountain View (CA); Hybrid; USD 180,000 - 220,000; Full time

Job summary

Acceler8 Talent is seeking a SoC Micro-Architect & RTL Designer for a hybrid role in Mountain View, CA, with on-site Tue–Thu. We’re a well-funded AI semiconductor startup building a processor architecture for frontier-scale language models, co-designing silicon and software around throughput, latency, memory, and interconnect demands.

You’ll translate architectural requirements into production‑quality microarchitecture and RTL, own blocks from spec to sign‑off, and optimize compute, memory, and

Qualifications

• 5+ years of SoC/ASIC microarchitecture and RTL design experience.
• Strong SystemVerilog skills; proficient with Python or C/C++.
• Experience delivering designs toward production silicon.
• Hands-on with synthesis, lint, CDC, and equivalence checking.
• Experience with high-performance compute, memory, or connectivity designs.
• Understanding RTL decisions impact on timing, power, area.

Responsibilities

• Translate architectural requirements into RTL and microarchitecture.
• Own subsystems from spec to sign-off.
• Develop compute, memory‑management, or high‑speed‑connectivity functionality.
• Optimize performance, power, area, and timing.
• Collaborate across verification, DFT, physical design, architecture, and software.
• Support silicon bring‑up and debug.

Skills

SoC microarchitecture

RTL design

SystemVerilog

Python

C/C++

Synthesis

Lint

CDC

Equivalence checking

Compute design

Memory design

Interconnect design

Tools

Python

SystemVerilog

Job description

Acceler8 Talent is seeking a SoC Micro-Architect & RTL Designer for a hybrid role in Mountain View, CA, with on-site Tue–Thu. We’re a well-funded AI semiconductor startup building a processor architecture for frontier-scale language models, co-designing silicon and software around throughput, latency, memory, and interconnect demands.

You’ll translate architectural requirements into production‑quality microarchitecture and RTL, own blocks from spec to sign‑off, and optimize compute, memory, and