Senior Silicon Engineer

Clera; San Francisco (CA); On-site; USD 200,000 - 300,000; Full time

Benefits offered by this job

Visa sponsorship available

Job summary

Clera is a well-funded AI accelerator startup seeking a founding silicon team member to lead the full journey of a custom XPU—from FPGA prototype through tapeout and bring‑up. You will set technical direction across architecture, RTL, verification, and tooling as the silicon organization grows.

Responsibilities include leading FPGA prototype development, guiding RTL for the first ASIC, and building comprehensive flows for rapid iteration and tapeout readiness. Visa sponsorship available.

Qualifications

• 8+ years hands-on digital design or silicon engineering experience (RTL, FPGA, or ASICs).
• Proven ability to ship SystemVerilog/Verilog in production silicon or FPGA.”
• End-to-end FPGA experience: RTL through place-and-route to hardware.
• Strong fundamentals in pipelines, clocks, resets, latency, throughput.
• Fluency with simulation, linting, synthesis, timing, and CDC verification flows.
• Experience automating hardware flows using Python, Tcl, Make, or similar.
• Background in AI accelerators or low-level AI kernel work.
• Tapeout, high-speed interface design, formal verification, UVM, cocotb, firmware or systems programming is a bonus.

Responsibilities

• Lead FPGA prototype development and optimize the XPU from spec to working silicon.
• Design and review RTL for the first ASIC, ensuring clean microarchitecture and synthesizable code.
• Build lint, simulation, synthesis, timing, and verification flows for rapid iteration and tapeout readiness.
• Make architecture decisions across compute datapaths, memory, interconnect, and control logic.
• Drive tapeout, bring-up, and delivery milestones, including critical sprints.
• Grow and mentor the silicon team as the company scales.

Tools

SystemVerilog

Verilog

RTL design

FPGA prototyping

ASIC development

Python scripting

Tcl

Make

Nix

UVM

Cocotb

Formal verification

CDC verification

Synthesis

Timing closure

Linting

SDC constraints

Tapeout

High-speed interfaces

Firmware

Systems programming

Job description

About the Role

As a founding silicon team member at a well-funded AI accelerator startup, you will lead the full journey of a custom XPU from FPGA prototype through tapeout and bring-up. This is a high-ownership, high-impact role that sets technical direction across architecture, RTL, verification, and tooling while the silicon organization grows around you.

What You'll Do

• Lead FPGA prototype development and optimization of the XPU, taking designs from specification to working silicon.

• Design and review RTL destined for the first ASIC, ensuring clean microarchitecture and synthesizable code.

• Build lint, simulation, synthesis, timing, and verification flows to support rapid iteration and tapeout readiness.

• Make architecture decisions spanning compute datapaths, memory systems, on-chip interconnect, and control logic.

• Drive the design through tapeout, bring-up, and delivery milestones, including critical-sprint periods.

• Grow and mentor the silicon team as the company scales.

What We're Looking For

• 8 or more years of hands‑on digital design or silicon engineering experience building RTL, FPGA prototypes, or ASICs.

• Proven ability to ship synthesizable SystemVerilog or Verilog in production silicon or FPGA designs.

• End‑to‑end FPGA experience: RTL through synthesis, place‑and‑route, and deployment to working hardware.

• Strong fundamentals in pipelining, clocks, resets, latency, throughput, and microarchitecture.

• Fluency with simulation, linting, synthesis, SDC constraints, timing closure, and CDC verification flows.

• Experience automating hardware flows using Python, Tcl, Make, Nix, or similar tools.

• Background designing or optimizing AI accelerators or low‑level AI kernel implementations.

• Tapeout experience, high‑speed interface design, formal verification, UVM, cocotb, firmware, or systems programming are strong advantages.

• Self-directed, comfortable with ownership, and energized by fast‑moving environments.

Compensation & Benefits

Base salary range: $200,000 to $300,000 USD annually, plus equity. Visa sponsorship is available.

Location

Full-time, on-site in San Francisco, CA. This role is not remote or hybrid.