XPU Architect

Conductor; Austin, Boston, San Francisco (TX, MA, CA); Hybrid; USD 150,000 - 230,000; Full time

Job summary

Conductor is seeking an XPU Architect to own the compute engine architecture for the A-0 and A-1 systems in Austin, TX. The role involves leveraging existing 3rd party IP creatively to address bandwidth and memory interface challenges.

The ideal candidate will have deep expertise in AI workloads, low latency LLM inference, and silicon implementation constraints, with a track record of owning high‑performance ASIC projects. Future generations will be semi-custom and custom designs.

Qualifications

• Experience architecting and owning a high performance, high TDP ASIC.
• Knowledge of computer architecture and silicon implementation constraints.
• Deep understanding of AI workloads, especially low latency LLM inference.
• Understanding of workload and system bottlenecks for interconnect, memory, bandwidth, latency.

Responsibilities

• Own the XPU compute engine architecture for the A-0 and A-1 systems.
• Heavily leverage existing 3rd party IP in a creative way to solve bandwidth and memory challenges.
• Contribute to semi-custom and custom designs for future generations.

Skills

High-performance ASIC architecture

AI workloads & LLM inference

System-level bottlenecks analysis

Memory bandwidth optimization

Job description

We’re looking for an XPU Architect to own the XPU compute engine architecture of the A-0 and A-1 systems. This will initially involve heavily leveraging existing 3rd party IP, but in a creative way to solve the bandwidth demand challenges and memory system interface challenges. Future generations of the compute XPU will be semi-custom and custom designs.

Ideal Background:

An ideal candidate will have:

• Previous experience architecting and owning a high performance, high TDP ASIC (eg AI chips, network switch chips, high performance CPUs or similar)
• Knowledge of both computer architecture but also silicon implementation, and understanding of the realistic constraints that silicon implementation places upon architectural options
• Deep understanding of AI workloads, especially low latency LLM inference
• Understanding of workload and system level bottlenecks, especially around inference, as it pertains to interconnect, memory capacity, bandwidth, latency, etc.

Strongly Preferred:

• Hands-on experience with AI chip architecture and tapeouts
• End to end ownership of at least one AI ASIC project
• History of product delivery (regardless of ultimate commercial success of said product)
• Experience with HBM-based AI chip architecture
• Experience in proposing “weird” chip architectures (in any domain, not just AI!)