Lead Signal & Power Integrity Architect

Advanced Micro Devices, Inc.; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Advanced Micro Devices, Inc. in San Jose is seeking a Principal Engineer to lead Signal and Power Integrity across SI/PI strategy, solving complex design challenges for FPGA and adaptive computing products.

You will mentor engineers, collaborate with Architecture, Package, PCB, Silicon teams, and drive decisions from simulation to hardware validation.

Candidates will have strong lab measurement skills and deep expertise in memory interfaces and high-speed signaling.

Qualifications

• Strong SI/PI expertise with hands-on lab experience.
• Ability to drive complex design decisions across teams.
• Experience with high-speed memory interfaces (DDR4/DDR5, LPDDR, HBM).
• Proven mentorship and technical leadership.
• Proficient in Python, C++, and Matlab.

Responsibilities

• Develop SI/PI strategies and guidelines across chips, packages, boards.
• Perform end-to-end simulations for high-speed interfaces.
• Lead DDR4/DDR5, LPDDR4/LPDDR5, and HBM analyses.
• Correlate simulations with lab measurements and debug.
• Mentor junior engineers and guide design tradeoffs.
• Collaborate with architecture, design, and manufacturing teams.
• Evaluate future package and PCB technologies for FPGA products.
• Drive cross-functional decisions through the product lifecycle.

Skills

Signal Integrity

Power Integrity

Lab measurements

Python

C++

Matlab

EM theory

DDR4/DDR5

Education

MS or PhD in Electrical Engineering

Tools

ADS

HFSS

SIwave

HSPICE

Job description

Advanced Micro Devices, Inc. in San Jose is seeking a Principal Engineer to lead Signal and Power Integrity across SI/PI strategy, solving complex design challenges for FPGA and adaptive computing products.

You will mentor engineers, collaborate with Architecture, Package, PCB, Silicon teams, and drive decisions from simulation to hardware validation.

Candidates will have strong lab measurement skills and deep expertise in memory interfaces and high-speed signaling.