Senior ASIC Design Engineer — High-Speed PCIe & Ethernet

Broadcom Inc.; Irvine (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Health, dental, vision

401(k) with company match

Employee Stock Purchase Program (ESPP)

Paid holidays

Paid time off

Job summary

Broadcom Inc. is seeking an experienced engineer to conceive and develop leadership silicon technology for data centers and cloud operators.

You will join a highly skilled team working on PCIe and other host interfaces to deliver high-throughput, power-efficient Ethernet devices across multiple generations. The role requires a BSEE with 8+ years (or MSEE with 6+ years) in high-speed chip architecture/RTL design, with strong Ethernet/PCIe background, ASIC experience, and scripting in Python or

Qualifications

• BSEE with 8+ years in high-speed chip architecture and RTL design; or MSEE with 6+ years.
• Strong background in Ethernet controller or PCIe.
• Hands-on ASIC design: architecture, RTL coding, simulation/verification, synthesis, timing closure, silicon validation.
• Strong communication and documentation skills; scripting in Python/Perl.

Responsibilities

• Work with global design/architecture teams to develop a leading-world device.
• Involve front-end design and potential for technical leadership across generations.
• Contribute to PCIe and other host interfaces for high-throughput, power-efficient Ethernet products.

Skills

Ethernet PCIe expertise

RTL design

ASIC design

Scripting (Python/Perl)

Education

Bachelor’s in Electrical Engineering

Master’s in Electrical Engineering

Tools

Python

Perl

Job description

Broadcom Inc. is seeking an experienced engineer to conceive and develop leadership silicon technology for data centers and cloud operators.

You will join a highly skilled team working on PCIe and other host interfaces to deliver high-throughput, power-efficient Ethernet devices across multiple generations. The role requires a BSEE with 8+ years (or MSEE with 6+ years) in high-speed chip architecture/RTL design, with strong Ethernet/PCIe background, ASIC experience, and scripting in Python or