Physical Design Engineer

Apple, Inc.; Melbourne (FL); On-site; USD 140,000 - 210,000; Full time

Job summary

Apple is seeking a forward-thinking Physical Design Engineer in Melbourne, FL to contribute across RTL to final GDSII, collaborating with architecture, CAD, timing and logic teams to deliver outstanding PHY designs. You will generate timing constraints, build floor-plans, perform block-level P&R, and fix timing, power and EM/IR issues, while guiding CAD methodologies and chip integration.

The ideal candidate has deep PHY or SoC design experience, Verilog and scripting skills, and fluency with

Qualifications

• Bachelor's degree in Electrical Engineering and at least 10 years of relevant industry experience.

Responsibilities

• Generate block/chip level static timing constraints.
• Build full chip floor-plan including pin placement, partitions and power grid.
• Perform block level place and route and close the design to meet timing, area and power constraints.
• Generate and Implement ECOs to fix timing, noise and EM IR violations.
• Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers.
• Participate in establishing CAD and physical design methodologies for correct by construction designs.
• Assist in flow development for chip integration.

Skills

PHY design

SoC design

Floorplanning

Place & Route

Power-grid design

Clock specification

Scripting Perl/Tcl

LVS/DRC expertise

Education

B.S. Electrical Engineering

Tools

Verilog HDL

EDA tools

Scripting Perl/Tcl

LVS/DRC debugging

Job description

At Apple we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. In this role, we will be at the center of a PHY design effort working with architecture, CAD, timing and logic design teams, with a critical impact on delivering outstanding PHY designs. You will be required to do physical designs of outstanding PHY design.

Description

As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.

Responsibilities

• Generate block/chip level static timing constraints.
• Build full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines.
• Perform block level place and route and close the design to meet timing, area and power constraints.
• Generate and Implement ECOs to fix timing, noise and EM IR violations.
• Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers.
• Participate in establishing CAD and physical design methodologies for correct by construction designs.
• Assist in flow development for chip integration.

Minimum Qualifications

• Bachelor's of Science in Electrical Engineering and a minimum of 10 years of relevant industry experience or equivalent.

Preferred Qualifications

• The ideal candidate will have deep design experience in high PHY and/or SOC designs.
• Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route.
• Experience in developing and implementing Power-grid and Clock specifications.
• Strong understanding of all aspects of Physical construction, Integration and Physical Verification.
• Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes Power user of industry standard Physical Design & Synthesis tools.
• Deep Understanding of scripting languages such as Perl/Tcl, solid understanding of Extraction and STA methodology and tools.
• Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong. Learn about accessibility in Apple’s workplace Learn about reasonable accommodations for job applicants

Apple accepts applications to this posting on an ongoing basis.