Senior Physical Design Engineer - High-Performance PHY/SOC

Apple, Inc.; Melbourne (FL); On-site; USD 140,000 - 210,000; Full time

Job summary

Apple is seeking a forward-thinking Physical Design Engineer in Melbourne, FL to contribute across RTL to final GDSII, collaborating with architecture, CAD, timing and logic teams to deliver outstanding PHY designs. You will generate timing constraints, build floor-plans, perform block-level P&R, and fix timing, power and EM/IR issues, while guiding CAD methodologies and chip integration.

The ideal candidate has deep PHY or SoC design experience, Verilog and scripting skills, and fluency with

Qualifications

• Bachelor's degree in Electrical Engineering and at least 10 years of relevant industry experience.

Responsibilities

• Generate block/chip level static timing constraints.
• Build full chip floor-plan including pin placement, partitions and power grid.
• Perform block level place and route and close the design to meet timing, area and power constraints.
• Generate and Implement ECOs to fix timing, noise and EM IR violations.
• Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers.
• Participate in establishing CAD and physical design methodologies for correct by construction designs.
• Assist in flow development for chip integration.

Skills

PHY design

SoC design

Floorplanning

Place & Route

Power-grid design

Clock specification

Scripting Perl/Tcl

LVS/DRC expertise

Education

B.S. Electrical Engineering

Tools

Verilog HDL

EDA tools

Scripting Perl/Tcl

LVS/DRC debugging

Job description

Apple is seeking a forward-thinking Physical Design Engineer in Melbourne, FL to contribute across RTL to final GDSII, collaborating with architecture, CAD, timing and logic teams to deliver outstanding PHY designs. You will generate timing constraints, build floor-plans, perform block-level P&R, and fix timing, power and EM/IR issues, while guiding CAD methodologies and chip integration.

The ideal candidate has deep PHY or SoC design experience, Verilog and scripting skills, and fluency with