Senior HBM SoC RTL Design Engineer

Micron; Richardson (TX); On-site; USD 181,000 - 323,000; Full time

Benefits offered by this job

Benefits package

Equity

Paid time off

Job summary

Micron Technology in the United States is seeking a senior SoC Design Engineer to help design and integrate the next-generation HBM logic die. You will collaborate with architecture, verification, physical design, firmware and product teams to deliver high-performance RTL implementations.

The role requires strong SystemVerilog, RTL, and experience with RTL-to-GDS flows, plus pre/post-silicon support. Expect a hands-on position with cross-functional collaboration, focusing on power, timing, and

Qualifications

• Degree in electrical or computer engineering or related field required.
• Proficiency in SystemVerilog/Verilog and RTL integration methodologies.
• Experience with RTL-to-GDS flow: synthesis, timing analysis, sign-off.
• Familiarity with Cadence, Synopsys, and/or Siemens EDA tools.
• Programming or scripting skills (Python, TCL, Perl, shell).

Responsibilities

• Design and implement RTL for SoC-level blocks used in HBM logic die.
• Integrate internal and third-party IP (controllers, NOC, MBIST, PHY).
• Collaborate with SoC architects to translate specs into RTL implementations.
• Participate in SoC-level integration: clocking, reset, power intent, config.
• Assist with pre-silicon validation and post-silicon bring-up, root-cause analysis.
• Contribute to design docs, block specs, and design reviews.

Skills

SystemVerilog/Verilog

RTL integration

Synthesis/STA

Python/TCL/Perl

SoC integration methods

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Tools

Cadence

Synopsys

Siemens

Job description

Micron Technology in the United States is seeking a senior SoC Design Engineer to help design and integrate the next-generation HBM logic die. You will collaborate with architecture, verification, physical design, firmware and product teams to deliver high-performance RTL implementations.

The role requires strong SystemVerilog, RTL, and experience with RTL-to-GDS flows, plus pre/post-silicon support. Expect a hands-on position with cross-functional collaboration, focusing on power, timing, and