HBM Physical Design Lead – End-to-End Optimizer

Micron Technology, Inc.; Texas; On-site; USD 180,000 - 240,000; Full time

Job summary

Micron Technology, Inc. is seeking an experienced physical design lead for HBM memory dies in Texas.

You will own floorplanning, power integrity, timing closure, and signoff across advanced HBM projects, collaborating with memory design, RTL, and packaging teams to optimize bandwidth, latency and reliability. The role requires 7+ years in advanced-node physical design, a strong background in STA, IR/EM, and PDN, and fluency with Cadence Innovus and Synopsys ICC2/Fusion Compiler.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field.

Responsibilities

• Drive end‑to‑end physical design for HBM base die and/or memory dies from netlist through GDSII.
• Own floorplanning, power planning, placement, CTS, routing, and signoff for HBM designs with very high macro density.
• Define and drive HBM‑specific physical architecture, including channel partitioning, PHY placement, and TSV keep‑out regions.
• Work with design to make architecture‑level tradeoffs to optimize bandwidth, latency, power, and yield.
• Assist power delivery network (PDN) design for extremely high current density environments.
• Drive IR drop, EM, and thermal closure across all operating modes.
• Ensure compliance with foundry reliability rules, including EM lifetime, via density, and TSV stress considerations.
• Own timing closure across corners for high‑speed internal logic and HBM PHY interfaces.
• Partner with clocking and PHY teams on clock distribution, skew control, and jitter sensitivity.
• Collaborate with packaging teams on 2.5D interposer‑based integration and HBM stack interfaces.
• Ensure physical alignment of micro‑bumps, TSVs, RDLs, and keep‑out zones.
• Own physical signoff readiness: STA, IR/EM, SI, DRC, LVS, density, and reliability.
• Bringing to bear AI in LVS/DRC fix automation throughout the build phase.
• Lead ECO strategies, including late‑stage timing and power fixes.
• Act as a key technical voice in tape‑out and executive design reviews.
• Partner with memory design, PHY, RTL, synthesis, DFT, SI, packaging, and test teams.
• Influence memory architecture and interface definitions to improve physical feasibility.
• Mentor senior and developing engineers; establish HBM‑specific PD guidelines and methodology.
• Drive flow improvements, automation, and reuse across HBM generations.

Skills

Floorplanning

Timing closure

Power integrity

Thermal awareness

Team leadership

Problem solving

Scripting (Tcl/Python)

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Cadence Innovus

Synopsys ICC2

Fusion Compiler

PrimeTime STA

RedHawk

Calibre DRC/LVS

Job description

Micron Technology, Inc. is seeking an experienced physical design lead for HBM memory dies in Texas.

You will own floorplanning, power integrity, timing closure, and signoff across advanced HBM projects, collaborating with memory design, RTL, and packaging teams to optimize bandwidth, latency and reliability. The role requires 7+ years in advanced-node physical design, a strong background in STA, IR/EM, and PDN, and fluency with Cadence Innovus and Synopsys ICC2/Fusion Compiler.