Lead HBM/GDDR Validation Engineer – Memory Subsystem

NVIDIA Corporation; Santa Clara (CA); On-site; USD 168,000 - 322,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation in Santa Clara, CA seeks an experienced hardware engineer to lead memory subsystem development from first silicon power-on to production.

You will drive HBM/GDDR enablement, validate designs, and develop robust test plans, partnering with memory vendors and cross-functional teams to ship memory into production.

The role requires 10+ years in high-speed DRAM and a Master’s in EE, with hands-on hardware and software skills; level 4/5 base salaries plus equity.

Qualifications

• Masters or higher in Electrical Engineering (or equivalent).
• 10+ years of hands-on high-speed DRAM design and test.
• Broad knowledge of ASIC design, mixed signal design, and power/signal integrity.
• Strong data analysis and problem-solving skills.
• Willingness to work hands-on with hardware and software.

Responsibilities

• Lead HBM/GDDR enablement, validation, and failure analysis for NVIDIA’s datacenter and graphics products.
• Drive review of memory partner’s design limits and test methodology.
• Integrate learnings into characterization and test plans for each memory generation.
• Apply understanding of controller design, board design, and DRAM design to define/test POR set methodologies.
• Work closely with memory partners to enable memory into production.
• Collaborate cross-functionally with multiple hardware design and software teams.
• Guide product-level decisions for memory subsystems spanning ASIC/VLSI/Board/ATE.

Skills

High-speed DRAM design

Data analysis

Linux scripting

Hardware debugging

Cross-functional collaboration

Power integrity

Education

Master's degree in Electrical Engineering

Job description

NVIDIA Corporation in Santa Clara, CA seeks an experienced hardware engineer to lead memory subsystem development from first silicon power-on to production.

You will drive HBM/GDDR enablement, validate designs, and develop robust test plans, partnering with memory vendors and cross-functional teams to ship memory into production.

The role requires 10+ years in high-speed DRAM and a Master’s in EE, with hands-on hardware and software skills; level 4/5 base salaries plus equity.