Post-Silicon Memory Validation Lead (GDDR/LPDDR/HBM)

NVIDIA Corporation; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Flexible time off

Continuous learning

Job summary

NVIDIA Corporation is seeking a senior memory engineer to lead high‑speed memory interface bring‑up and qualification on GPU/SoC silicon in Santa Clara, CA. You will own validation, IO tuning, timing margins, and multi‑vendor DRAM qualification across GDDR, LPDDR, and HBM.

You will design AI‑enabled workflows for margin analysis and failure triage, collaborate with pre‑Si teams and DV groups, and coordinate with DRAM vendors and manufacturing partners worldwide.

Qualifications

• B.Tech or M.Tech in Electrical, Electronics, or Computer Engineering (or equivalent experience).
• 10+ years in the semiconductor industry with at least 3 years directly on memory interface bring-up, characterization, and qualification on shipped silicon.
• Deep protocol and physical-layer understanding of GDDR, LPDDR, or HBM with calibration, IO tuning, timing margin, and vendor differences.
• Strong hands-on lab fundamentals with oscilloscope, DMM, thermal chambers, protocol analyzers, and knowledge of PCB stack-up and SI/PI guidelines.
• Demonstrated AI-driven workflow for memory characterization, margin analysis, or failure triage with measurable impact.

Responsibilities

• Bring up high-speed memory interfaces on GPU/SoC silicon from first power-on through PVT characterization and productization.
• Own functional validation, IO tuning, timing margin analysis, and multi-vendor DRAM qualification across memory controller, PHY, and DRAM devices.
• Lead root-cause closure on the hardest memory failures spanning silicon, controller, PHY, package, board SI/PI, firmware, and workload, with reusable fixes.
• Design and deploy AI-enabled workflows for margin data analysis, shmoo bucketing, failure signature detection, and workload-vs-margin correlation.
• Partner with pre-Si architecture, design, and DV teams to translate new memory features into post-Si validation plans, feeding learnings back to pre-Si.

Skills

Memory bring-up

GDDR/LPDDR/HBM

Lab fundamentals

AI workflows

Education

Bachelor/Master in Electrical/Electronics/Computer Engineering

Tools

Oscilloscope

DMM

Thermal chambers

Job description

NVIDIA Corporation is seeking a senior memory engineer to lead high‑speed memory interface bring‑up and qualification on GPU/SoC silicon in Santa Clara, CA. You will own validation, IO tuning, timing margins, and multi‑vendor DRAM qualification across GDDR, LPDDR, and HBM.

You will design AI‑enabled workflows for margin analysis and failure triage, collaborate with pre‑Si teams and DV groups, and coordinate with DRAM vendors and manufacturing partners worldwide.