Lead, HBM Memory Subsystem Validation

Advanced Micro Devices; Santa Clara (CA); On-site; USD 170,000 - 230,000; Full time

Job summary

AMD in Santa Clara, CA is seeking a Memory Sub-system Validation Lead to drive pre- and post-silicon validation of on-die HBM for the Datacenter GPU line. You will partner with DRAM, Memory Controller, DV, DDR PHY, DRAM product engineering and software teams to ensure memory designs meet quality standards.

As a hands-on leader, you will mentor engineers, develop test plans, and lead by example in a lab environment, delivering thorough validation results and clear defects to mass production.

Qualifications

• Bachelors or Masters in Electrical or Computer Engineering.
• Experience with pre- and post-silicon validation of memory subsystems.
• Hands-on with lab tools and debugging in a hardware lab.

Responsibilities

• Lead pre- and post-silicon validation planning, execution and debug for HBM memory.
• Develop and execute functional and electrical validation test plans.
• Interface with DRAM architecture, Memory Controller Design, DV, DDR PHY, DRAM product engineering, and software teams.

Skills

Leadership

Debugging

Communication

C/C++

Python

Lab Tools

Education

Bachelors or Masters in Electrical or Computer Engineering

Tools

JTAG

I2C

Tester

Lab equipment

Job description

AMD in Santa Clara, CA is seeking a Memory Sub-system Validation Lead to drive pre- and post-silicon validation of on-die HBM for the Datacenter GPU line. You will partner with DRAM, Memory Controller, DV, DDR PHY, DRAM product engineering and software teams to ensure memory designs meet quality standards.

As a hands-on leader, you will mentor engineers, develop test plans, and lead by example in a lab environment, delivering thorough validation results and clear defects to mass production.