HBM Memory Subsystem Validation Lead

AMD; Santa Clara (CA); On-site; USD 180,000 - 230,000; Full time

Job summary

AMD Santa Clara seeks a dynamic Memory Sub-system Validation Lead for pre- and post-silicon work on HBM in Datacenter GPUs. You will drive validation plans, collaborate with DRAM, memory controller, DV, PHY, and software teams, and mentor engineers in a lab-driven environment.

You are expected to lead with strong test execution, debugging, and deliverables while navigating complex hardware-software interactions across ML/HPC workloads.

Qualifications

• Leadership experience with multi-disciplinary teams and strong communication skills.
• Proven debugging skills and ability to drive issue resolution under pressure.
• Hands-on memory validation, post-silicon characterization and test-plan execution.

Responsibilities

• Lead pre- and post-silicon validation for HBM memory subsystems in AMD datacenter GPUs.
• Develop test plans for functional, electrical validation and PVT shmoo characterization.
• Collaborate with DRAM, memory controller, DV, PHY, and software teams to drive quality.
• Mentor junior engineers and guide cross-functional teams to root-cause issues.

Skills

Leadership

Debugging

C/C++

Python

Lab tools

Linux

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

JTAG

I2C

Lab testers

Lab equipment

Windows/Linux

Job description

AMD Santa Clara seeks a dynamic Memory Sub-system Validation Lead for pre- and post-silicon work on HBM in Datacenter GPUs. You will drive validation plans, collaborate with DRAM, memory controller, DV, PHY, and software teams, and mentor engineers in a lab-driven environment.

You are expected to lead with strong test execution, debugging, and deliverables while navigating complex hardware-software interactions across ML/HPC workloads.