Memory Subsystem HW Validation Engineer | Equity

NVIDIA Corporation; Santa Clara (CA); On-site; USD 108,000 - 213,000; Full time

Job summary

NVIDIA Corporation in Santa Clara, CA is seeking a hardware engineer to drive memory subsystem bringup and validation from first silicon power-on to production. You will plan DDR memory tuning, review specs, and debug issues across silicon, board, and firmware domains.

The role requires 2+ years of experience, a BS/MS in EE, strong signal integrity knowledge, and programming familiarity (C/C++/Python). You will collaborate across teams and work across time zones.

Qualifications

• BS or MS EE degree with affinity for mixed signal/analog, embedded systems, and digital design (or equivalent experience).
• 2+ years relevant experience.
• Understanding of high speed signal integrity and experience with oscilloscopes.
• Understanding of schematic capture and board design.
• Working knowledge of PC systems, Windows OS, and Linux.
• Excellent understanding of EE fundamentals.
• Able to break problems down based on first principles.
• Familiar with scripting or programming languages such as C, C++, JAVA, Python, or Perl.
• Possess good collaboration and cross-disciplinary teamwork skills.
• Comfortable working across time zones.
• Deeply curious about technology and passionate about learning.

Responsibilities

• Planning and performing DDR memory tuning, validation, and feature enablement on NVIDIA products.
• Reviewing silicon design specifications, component datasheets, board schematics, and layout.
• Debugging and resolving controller, memory, board, or software/firmware issues at all stages of the product.
• Refining memory bringup and validation strategy.
• Providing feedback and recommendations to silicon, board, and software teams.

Skills

Signal integrity

Hardware debugging

Collaboration

Time-zone coordination

Curiosity for technology

Education

BS or MS EE degree

Tools

Oscilloscope

Schematic capture tools

PCB design

Job description

NVIDIA Corporation in Santa Clara, CA is seeking a hardware engineer to drive memory subsystem bringup and validation from first silicon power-on to production. You will plan DDR memory tuning, review specs, and debug issues across silicon, board, and firmware domains.

The role requires 2+ years of experience, a BS/MS in EE, strong signal integrity knowledge, and programming familiarity (C/C++/Python). You will collaborate across teams and work across time zones.