FPGA Engineering Manager (Nextest, Tualatin, OR)

Teradyne; Tualatin (OR); On-site; USD 171,000 - 273,600; Full time

Benefits offered by this job

Health and well‑being benefits

Medical insurance

Dental insurance

Vision insurance

Retirement savings plan

Life and disability insurance

Paid vacation & holidays

Tuition assistance

Job summary

Teradyne's Memory Test Division in Tualatin, OR is seeking an experienced FPGA Engineering Manager to lead a small team and deliver advanced memory test solutions, combining digital and analog design with PCIe, DDR, and SERDES interfaces.

You will plan multiple FPGA projects, mentor 4–6 engineers, collaborate across hardware, software, and firmware, and drive architectural reviews, RTL coding, and lab validation to ensure on-time delivery.

Qualifications

• 12+ years in Digital ASIC or FPGA design.
• 5+ years as FPGA/ASIC project lead, driving multiple projects.
• Experience coding RTL (Verilog).
• Experience with PCIe, DDR3/4/5, AXI, Ethernet, SPI, SERDES.
• Proficient in Vivado/Quartus tools.

Responsibilities

• Plan and manage multiple FPGA projects to on-time delivery.
• Represent FPGA team on core teams and program reviews.
• Provide support for sustaining issues.
• Collaborate with hardware, software, and firmware for integration.
• Recruit, onboard, and retain engineers to build a high-performing team.
• Set goals and conduct performance conversations for 4–6 engineers.
• Contribute to FPGA process improvement initiatives.
• Provide hands-on guidance on architectures, designs, and specs.
• Participate in RTL coding, synthesis, timing closure, and lab validation.

Skills

RTL Verilog

STA tools

PCIe

DDR3/4/5

AXI

SERDES

Vivado/Quartus

UVM

Git/CI

Education

B.S./M.S. in Electrical Engineering

Tools

Cadence

Vivado

Quartus

Lint

CDC

Git

CI pipelines

Job description

FPGA Engineering Manager (Memory Test, Tualatin, OR)

Date: Jul 13, 2026

Location: Tualatin, OR, US

Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Manager to support the development of our growing portfolio of cutting‑edge memory test solutions.

MTD creates advanced solutions for complex testing applications, driving innovation through creativity and diverse perspectives. Our test instrumentation supports the world’s most advanced memory technologies, combining state‑of‑the‑art digital and analog designs, cutting‑edge ASIC/FPGA technologies, liquid cooling, and high‑performance signal delivery.

Your Key Responsibilities

• Plan, prioritize, and manage multiple FPGA development projects, ensuring on‑time delivery within budget and scope.
• Represent the FPGA team on project core teams and at program reviews.
• Provide support for sustaining issues.
• Work closely with cross‑functional teams, including hardware, software, and firmware engineers, to ensure seamless integration of FPGA designs into larger systems.
• Recruit, onboard, and retain top engineering talent to build a high‑performing team.
• Set goals and conduct regular performance conversations for a team of 4 to 6 engineers.
• Contribute to FPGA team process improvement initiatives.
• Provide hands‑on technical guidance to the FPGA engineering team, including reviewing and contributing to FPGA architectures, designs, and specifications.
• Actively participate in FPGA design and development, including RTL coding, synthesis, timing closure, and lab validation.

All About You

• B.S. or M.S. in Electrical Engineering or closely related discipline
• 12+ years of relevant experience in Digital ASIC or FPGA design
• Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through concept development, architectural exploration, design implementation, lab validation, and production release.
• Extensive experience coding RTL (Verilog preferred).
• Extensive experience using digital simulation tools (Cadence preferred).
• Extensive experience using static timing analysis tools.
• Experience designing with PCIe, DDR3/4/5, AXI, Ethernet, SPI, SERDES.
• Experience with either AMD or Altera FPGAs and development tools (Vivado/Quartus), preferably both.
• Experience using digital design quality tools, e.g., Lint, CDC.
• Experience with bug tracking tools.
• Experience with source control systems and continuous integration.
• Familiarity with digital verification tools and methodologies (preferably UVM).
• Experience with project scheduling tools.
• Excellent presentation and communication skills.

Additional Desired Skills

• Experience developing hardware for automated test equipment
• Experience as a first‑level manager of an engineering team.
• Experience with FPGA transceiver‑based designs
• Experience with DRAM and flash memory interfaces
• Experience with Linux and Windows operating systems
• Familiarity with ATE instrumentation

Compensation

The base salary range for this role is $171,000 - $273,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan

This job is eligible for discretionary bonus(es) based on financial performance.

Benefits

Teradyne offers a variety of robust health and well‑being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.