Lead FPGA Architect for DoD Systems – Tucson Onsite

Raytheon; Albuquerque (NM); On-site; USD 132,000 - 252,000; Full time

Benefits offered by this job

Relocation

Job summary

Raytheon’s Effector Digital Products team in Tucson is seeking a Senior Principal FPGA Design Engineer to lead FPGA architecture and design across vendors such as Xilinx, Altera, and Microsemi, using VHDL.

This on-site role requires a DoD Secret clearance and offers a salary range from 132,400 USD to 251,600 USD, with extensive system-level responsibilities and mentorship of junior engineers.

Qualifications

• Requires STEM degree with 10+ years of relevant experience.
• System-level FPGA requirements specification and architecture development.
• Proposal experience including basis of estimate generation and resource planning.
• Strong design hand-off knowledge across system requirements, configurable logic, software, and tests.
• FPGA/ASIC design (VHDL/Verilog) or verification (SystemVerilog).
• Xilinx or Microsemi devices and flow tools.

Responsibilities

• Lead FPGA-based systems architecture and design, selecting parts and interfaces.
• Establish project processes and plans; drive schedules on time and budget.
• Mentor junior engineers and guide cross-functional teams through reviews and tests.
• Design, verify, and document complex configurable logic solutions for products.
• Translate system requirements into FPGA requirements and implement in VHDL/Verilog.
• Create verification plans and evidence of coverage; support customer interactions.

Skills

FPGA design

System architecture

Verilog/VHDL

Project leadership

Education

STEM degree

Tools

Xilinx devices

Microsemi devices

Job description

Raytheon’s Effector Digital Products team in Tucson is seeking a Senior Principal FPGA Design Engineer to lead FPGA architecture and design across vendors such as Xilinx, Altera, and Microsemi, using VHDL.

This on-site role requires a DoD Secret clearance and offers a salary range from 132,400 USD to 251,600 USD, with extensive system-level responsibilities and mentorship of junior engineers.