Senior FPGA Design Engineer Onsite Tucson Secret Clearance

Raytheon; Tucson (AZ); On-site; USD 87,000 - 165,000; Full time

Benefits offered by this job

Relocation Assistance

9/8 Schedule - every other Friday off!

Job summary

Raytheon in Tucson, AZ is seeking a Senior FPGA Design Engineer to develop FPGA designs for Xilinx, Altera (Intel), and Microsemi devices using VHDL and Verilog. The role involves collaborating with hardware and systems engineers to meet specifications across RF, EO DSP, and data interfaces.

Responsibilities include translating system requirements into FPGA requirements, performing verification with directed and constrained random tests, and producing comprehensive design documentation.

Qualifications

• Degree in STEM with 5+ years of FPGA experience.
• Experience with VHDL and/or Verilog coding.
• Experience with SystemVerilog coding.
• Experience with Xilinx or Microsemi devices and flow tools.

Responsibilities

• Design and deliver production-quality FPGA releases from proof of concept to production.
• Architect FPGA-based systems and determine parts, interfaces, and CONOPS.
• Translate system requirements into FPGA requirements.
• Code in VHDL for reliability and maintainability.
• Verify designs with directed and constrained random tests and coverage.
• Lead small teams and mentor engineers.
• Create documentation including requirements and verification plans.

Skills

VHDL

Verilog

SystemVerilog

Xilinx

Microsemi

FPGA design

Education

Bachelor's degree in STEM

Tools

Xilinx tools

Microsemi tools

Job description

Raytheon in Tucson, AZ is seeking a Senior FPGA Design Engineer to develop FPGA designs for Xilinx, Altera (Intel), and Microsemi devices using VHDL and Verilog. The role involves collaborating with hardware and systems engineers to meet specifications across RF, EO DSP, and data interfaces.

Responsibilities include translating system requirements into FPGA requirements, performing verification with directed and constrained random tests, and producing comprehensive design documentation.