Lead Emulation Test Engineer Palladium, Remote

Positron; United States; Remote; USD 180,000 - 300,000; Full time

Benefits offered by this job

Health insurance

Life and disability coverage

Remote-first culture

Job summary

Positron AI is seeking an Emulation Test Engineer to own the end-to-end emulation strategy on Cadence Palladium for next-generation AI inference ASICs. You will architect multi-rack model builds, drive the left-shift of software development, and collaborate with RTL, DV, and Software teams to create high-performance virtual environments.

You will lead complex model builds, enable software teams to boot OS images, and validate PCIe Gen 6/7, 112G+VSR, and Ethernet interfaces while optimizing power

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.
• 8+ years in ASIC Emulation or Verification with large Palladium installations.
• Mastery of SystemVerilog/Verilog and C/C++ for transactor development.

Responsibilities

• Lead partitioning and compilation of design across multi-rack Palladium environment for performance and debug visibility.
• Create and maintain hybrid emulation and co-simulation environments (SCE-MI or DPI) to boot OS images and run AI workloads on pre-silicon hardware.
• Design and execute emulation test plans to verify high-speed interfaces (PCIe Gen 6/7, 112G+VSR, Ethernet) and AI memory hierarchies.
• Utilize Palladium Dynamic Power Analysis (DPA) and throughput monitors to identify true peaks and bottlenecks not captured by simulation.
• Act as primary technical point of contact with Cadence R&D to troubleshoot tools and leverage Palladium Z3 capabilities.

Skills

Palladium expertise

Python

Tcl

Bash

C/C++

SystemVerilog/Verilog

Verdi

SimVision

VIF

Python scripting

Education

BS/MS in Electrical/Computer Engineering or Computer Science

Tools

Cadence Palladium (Z1/Z2/Z3)

ICE (In-Circuit Emulation)

DPI/SCE-MI

Job description

Positron AI is seeking an Emulation Test Engineer to own the end-to-end emulation strategy on Cadence Palladium for next-generation AI inference ASICs. You will architect multi-rack model builds, drive the left-shift of software development, and collaborate with RTL, DV, and Software teams to create high-performance virtual environments.

You will lead complex model builds, enable software teams to boot OS images, and validate PCIe Gen 6/7, 112G+VSR, and Ethernet interfaces while optimizing power