ASIC Emulation & Verification Engineer

AnySilicon; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Anysilicon in San Jose, CA is seeking an experienced ASIC Emulation and Verification Engineer to bridge simulation and hardware acceleration. You will bring up complex ASIC IP/SoC designs on Cadence Palladium, convert RTL to emulation-ready models, and run high-speed hardware-accelerated validation.

Responsibilities include mapping RTL onto Palladium, debugging, and collaborating with firmware teams for early bring-up.

Qualifications

• Bachelor’s degree with minimum 8 years hardware description or verification experience.
• Master’s degree with minimum 6 years relevant experience.
• Experience with SystemVerilog and UVM preferred.

Responsibilities

• Map RTL databases onto Cadence Palladium hardware acceleration systems.
• Resolve compilation errors and manage clocking/memory overrides for full-chip and subsystem emulation models.
• Collaborate with firmware teams to accelerate early firmware bring-up on Palladium.
• Provide hardware models and configure virtual debuggers for bootloaders and drivers.
• Perform pre-silicon verification tasks using SystemVerilog and UVM, including test cases and debugging RTL issues.
• Diagnose hardware and environment issues on Palladium using advanced debugging features.
• Build and maintain automated scripts for compiling RTL databases and Palladium regressions.

Skills

SystemVerilog

UVM

Python

Automation

AMBA protocols

Education

Bachelor’s Degree in Electrical/Computer Engineering

Master’s Degree in related field

Tools

Cadence Palladium

Job description

We are looking for an experienced ASIC Emulation and Verification Engineer to enhance the transition between simulation and hardware acceleration. This role involves bringing up complex ASIC IP and SoC designs on Cadence Palladium emulation platforms, converting RTL databases into emulation-ready models, and executing high-speed hardware acceleration. The engineer will also support the core pre-silicon team with UVM-based simulation, verification closure, and debugging tasks.

Responsibilities:

• Compile, synthesize, and map complex RTL databases onto Cadence Palladium hardware acceleration systems.
• Resolve compilation errors and manage clocking/memory overrides for full-chip and sub-system emulation models.
• Collaborate with firmware engineering teams to accelerate early firmware bring-up on the Palladium platform.
• Provide hardware models and configure virtual debuggers to facilitate low-level bootloaders and drivers.
• Perform traditional pre-silicon verification tasks using SystemVerilog and UVM, including authoring test cases and debugging RTL anomalies.
• Diagnose complex hardware and environment issues on Palladium using advanced debugging features.
• Build and maintain automated scripts for compiling RTL databases and launching Palladium regressions.

Qualifications:

• Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field with a minimum of 8 years of hardware description or verification experience.
• Master’s Degree in a related field with a minimum of 6 years of relevant experience.

Skills:

• Deep hands-on experience with Cadence Palladium emulation platforms (e.g., Palladium Z1/Z2).
• Strong proficiency in hardware description languages (Verilog / SystemVerilog) and hardware synthesis concepts.
• Proven experience with UVM simulation frameworks, assertion-based testing, and metric-driven coverage closure.
• Expertise in scripting languages such as Python, Perl, Bash, or Tcl for automation and log file parsing.
• Solid understanding of AMBA subsystem protocols (AXI, AHB, APB) and processor interfaces.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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