Lead DV Engineer, ASIC Verification & Tapeout

Medium; Saratoga (CA); On-site; USD 120,000 - 220,000; Full time

Benefits offered by this job

Paid holidays

Paid time off

Health benefits

Legal services (US only)

Wellness program

Job summary

E-Space in Saratoga, CA is seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. You will build Verilog/SystemVerilog/UVM verification environments and debug RTL simulations end-to-end.

The role demands 10+ years in semiconductor verification, strong C/C++ for verification, and leadership in code coverage closure and tapeout projects. Base pay targets $120k-$220k annually; US work authorization required.

Qualifications

• Expert-level proficiency in Verilog and SystemVerilog.
• Proven experience building UVM verification environments from scratch.
• Deep understanding of verification methodologies and best practices

Responsibilities

• Write comprehensive test plans and maintain test suites.
• Debug complex RTL simulations and gate-level timing with SDF back-annotation.
• Lead design verification efforts through chip tapeout.

Skills

Verilog/SystemVerilog

UVM

C/C++

Python/Perl

RTL Debugging

Tools

Verilog

SystemVerilog

UVM

Job description

E-Space in Saratoga, CA is seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. You will build Verilog/SystemVerilog/UVM verification environments and debug RTL simulations end-to-end.

The role demands 10+ years in semiconductor verification, strong C/C++ for verification, and leadership in code coverage closure and tapeout projects. Base pay targets $120k-$220k annually; US work authorization required.