Application Specific Integrated Circuit Verification Engineer

Technical-Link N. America; San Diego (CA); Sur place; USD 120 000 - 180 000; Plein temps

Résumé du poste

Technical-Link N. America is seeking a Senior ASIC Verification Engineer with 8+ years of hands-on SystemVerilog and UVM experience to drive verification across IP, block, subsystem, and SoC levels. Satellite or DSP background is a plus but not required, and complex design debugging is essential.

The role emphasizes testbench development, scoreboards, reference models, and protocol monitors to ensure robust verification and signoff across multiple projects.

Qualifications

• Proficient in SystemVerilog and UVM verification across IP/Block/Subsystem/SoC levels.
• Experience in ASIC/SoC functional verification with testbench development.
• Strong skills in verification planning, assertions, and functional coverage closure.

Responsabilités

• Develop and maintain testbenches for IP/Block/Subsystem/SoC levels.
• Debug complex ASIC/SoC designs and drive verification to signoff.
• Create scoreboards, reference models, and protocol monitors for verification.
• Collaborate across teams on RTL debugging and datapath verification.

Connaissances

SystemVerilog

UVM

ASIC/SoC verification

Verification planning

Assertions

Functional coverage

Testbench development

Scoreboards

Reference models

Protocol monitors

RTL debugging

Datapath verification

Description du poste

Role: Senior ASIC Verification Engineer Industry: Satellite Communications / Semiconductor Experience: 8+ years Key requirement: Strong hands-on SystemVerilog and UVM verification experience.

What the client is looking for

• Multiple openings — candidates will be placed where their skills fit best.
• Three verification levels: IP/Block-level, Subsystem-level, and SoC-level.
• Well-rounded UVM engineers who can develop testbenches, debug complex designs, and drive verification to signoff.
• Space experience is a plus.
• DSP experience is a plus.

Must-have technical skills

• SystemVerilog and UVM.
• ASIC/SoC functional verification.
• Verification planning, assertions, and functional coverage closure.
• Testbench development, scoreboards, reference models, and protocol monitors.
• RTL and testbench debugging.
• Complex digital control and datapath verification.

Preferred experience

• Satellite, wireless, modem, or baseband communications.
• DSP pipelines, LDPC/BCH/FEC blocks, framing engines, or beamforming.
• Formal verification, CDC/RDC, low-power verification, and high-speed interfaces.
• Hardware/software integration and post-silicon debug.

A senior UVM verification engineer with 8+ years of ASIC/SoC experience, strong SystemVerilog skills, and experience at one or more verification levels. Satellite or DSP expertise is beneficial but not mandatory.