Senior ASIC DV Engineer — Tapeouts, UVM & Power

Qualcomm; Santa Clara (CA); On-site; USD 153,200 - 229,800; Full time

Benefits offered by this job

Competitive annual discretionary bonus

RSU grants

Accessible workplace

Support for individuals with disabilities

Job summary

A leading technology company in California is seeking an experienced ASIC Design Verification Engineer to oversee the verification lifecycle for digital power IPs. The ideal candidate will have at least 3 years of experience in verification roles and a Bachelor's degree or higher in related fields. This position offers a competitive salary range of $153,200.00 - $229,800.00 with additional benefits including a discretionary bonus program.

Qualifications

• Minimum 3 years of DV experience using UVM/assertion-based verification technologies.
• Experience in verifying complex SOC or SOC subsystems.
• Exposure to performance and power verification.

Responsibilities

• Complete verification lifecycle from system-level concept to tape out.
• Comprehensive pre-silicon test planning for digital power IPs.
• Develop automation to improve verification efficiency.

Skills

UVM

SystemVerilog

C++

Python

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Job description

A leading technology company in California is seeking an experienced ASIC Design Verification Engineer to oversee the verification lifecycle for digital power IPs. The ideal candidate will have at least 3 years of experience in verification roles and a Bachelor's degree or higher in related fields. This position offers a competitive salary range of $153,200.00 - $229,800.00 with additional benefits including a discretionary bonus program.