Senior DV Engineer for LEO Satellite ASIC Verification

Medium; Saratoga (CA); On-site; USD 120,000 - 220,000; Full time

Benefits offered by this job

Paid holidays

Paid time off

Optional legal services (US only)

Health and wellness options

Job summary

E-Space is seeking a Digital Design Verification Engineer to verify our custom ASICs for satellite and wireless telephony. Candidates should be proficient in Verilog, SystemVerilog, and UVM, with knowledge of C/C++ for verification and scripting in Perl or Python.

Leadership in verification at the block level is a plus for this role based in Saratoga, CA. We expect 6+ years of design verification experience in the semiconductor industry and offer a competitive base pay with total compensation

Qualifications

• HDL & Verification Methodology
• Strong proficiency in Verilog and SystemVerilog
• Experience writing tests within an existing UVM verification environment
• Solid understanding of UVM architecture and methodology
• Programming & Scripting: write C/C++ code for verification purposes
• Some scripting experience in Perl or Python
• Verification Planning & Execution: contribute to and help write test plans
• Experience writing and maintaining verification tests
• Ability to debug RTL simulations independently
• Leadership: experience leading design verification efforts at the block level
• Experience driving code coverage closure on assigned blocks

Responsibilities

• Lead design verification efforts at the block level
• Drive code coverage closure on assigned blocks
• Write and maintain verification tests
• Contribute to verification test plans

Skills

Verilog

SystemVerilog

UVM

C/C++

Perl or Python

Tools

VHDL

Job description

E-Space is seeking a Digital Design Verification Engineer to verify our custom ASICs for satellite and wireless telephony. Candidates should be proficient in Verilog, SystemVerilog, and UVM, with knowledge of C/C++ for verification and scripting in Perl or Python.

Leadership in verification at the block level is a plus for this role based in Saratoga, CA. We expect 6+ years of design verification experience in the semiconductor industry and offer a competitive base pay with total compensation