Lead DRAM Physical Design Engineer

Micron Technology, Inc.; Boise (ID); On-site; USD 180,000 - 240,000; Full time

Job summary

Micron Technology, Inc. in Boise, Idaho, is seeking a Principal Physical Design Engineer to lead advanced DRAM digital design implementation from RTL through tapeout, with a strong focus on timing closure, power integrity, EMIR analysis and reliability.

You will mentor engineers, drive methodology improvements, and collaborate with architecture, RTL, CAD, and technology teams to deliver PPA targets and scalable memory products for next-generation devices.

Qualifications

• Master's degree in Electrical Engineering with 8+ years of ASIC PD experience or Bachelor's with 10+ years.
• Hands-on experience with STA, signal integrity, power integrity, physical verification, and advanced process technologies.
• Strong scripting and automation skills using Python or Tcl.

Responsibilities

• Lead physical design implementation of complex DRAM digital designs, including floorplanning, place and route, clock tree synthesis, timing closure, and tapeout.
• Drive power integrity strategies and signoff methodologies, including PDN planning, IR drop analysis, EM verification, and EMIR signoff.
• Collaborate with multi-functional teams to resolve timing, congestion, power, signal integrity, and reliability challenges at block and full-chip levels.
• Develop and deploy methodology improvements, automation solutions, and guidelines to improve build quality, efficiency, and scalability.
• Mentor engineers and provide technical leadership while influencing future memory products through innovation in physical design and signoff methodologies.

Job description

Micron Technology, Inc. in Boise, Idaho, is seeking a Principal Physical Design Engineer to lead advanced DRAM digital design implementation from RTL through tapeout, with a strong focus on timing closure, power integrity, EMIR analysis and reliability.

You will mentor engineers, drive methodology improvements, and collaborate with architecture, RTL, CAD, and technology teams to deliver PPA targets and scalable memory products for next-generation devices.