Lead Digital Verification Engineer - FPGA & UVM

Openbound; Tualatin (OR); On-site; USD 155,000 - 248,000; Full time

Benefits offered by this job

Health benefits

Retirement plan

Paid vacation

Job summary

Teradyne is seeking a digital functional verification technical lead in Oregon to plan, strategize, and execute advanced FPGA verification projects. You will guide large cross-site teams and collaborate with hardware, software, and applications groups to ensure a robust verification flow.

Qualified candidates have 10+ years of relevant experience and mastery of SystemVerilog, UVM, and verification IP integration. Strong leadership and mentoring skills are essential in a fast-paced environment.

Qualifications

• Master's or Bachelor's degree with extensive relevant work experience as specified.
• Experience with verification planning and testbench architecture.
• Full verification cycle from design spec to closure.
• Proficient with SystemVerilog, UVM, assertions and functional coverage.
• Expertise with Verification IP integration and reference models.
• Experience with multiple protocols and regression analysis.
• Strong scripting and version-control experience.

Responsibilities

• Lead planning, strategy, and execution of FPGA verification projects.
• Provide technical leadership for large cross-site verification teams.
• Interface with hardware, software, and applications groups.
• Mentor junior engineers and coordinate teams across time zones.
• Drive verification progress to closure and issue resolution.

Skills

SystemVerilog

UVM

Verification planning

Testbench architecture

Functional coverage

Assertions

Constraint random testing

Verification IP integration

Reference models

Automation scripting

Python

Git

ClearCase

Time-zone collaboration

Leadership

Mentoring

Education

Master’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science

Bachelor’s Degree in Electrical Engineering/Computer Engineering/Computer Science

Tools

Git

ClearCase

SVN

Makefiles

Shell scripting

TCL

Python

Job description

Teradyne is seeking a digital functional verification technical lead in Oregon to plan, strategize, and execute advanced FPGA verification projects. You will guide large cross-site teams and collaborate with hardware, software, and applications groups to ensure a robust verification flow.

Qualified candidates have 10+ years of relevant experience and mastery of SystemVerilog, UVM, and verification IP integration. Strong leadership and mentoring skills are essential in a fast-paced environment.