FPGA Verification Engineer: SystemVerilog & UVM

Teradyne; Redding (CA); On-site; USD 99,000 - 158,000; Full time

Benefits offered by this job

Discretionary bonus

Health and well-being benefits

Tuition assistance

Job summary

Teradyne seeks a Digital Logic Verification Engineer to primarily verify FPGA designs, collaborating with cross‑functional teams to deliver robust, high‑quality solutions at our North Reading, MA development center.

The role emphasizes SystemVerilog/UVM test benches, coverage collection, and close interaction with logic designers to ensure design correctness and timely delivery. Experience with CI/CD workflows is a plus.

Qualifications

• 3+ years of professional experience in digital logic verification or related roles
• Experience with Cadence Xcelium or other industry‑standard simulators
• Strong experience with System Verilog and Universal Verification Methodology (UVM)
• Working knowledge of common IP protocols (e.g., SPI, AXI, DDR)
• Experience with RTL design using Verilog HDL
• Familiarity with System Verilog assertion‑based verification methodologies
• Experience working within CI/CD development flows

Responsibilities

• Review design requirements and specifications
• Write and review verification plans
• Develop testbench architecture and implementation
• Create reference models
• Write System Verilog tests and develop UVM environments; perform debug
• Collect, merge, and close functional and code coverage
• Manage bugs and issues using a tracking tool
• Collaborate closely with logic designers
• Communicate technical status and risks to the team leader

Skills

Cross-functional collaboration

Communication

Attention to detail

Tools

Cadence Xcelium

SystemVerilog

UVM

Verilog HDL

Job description

Teradyne seeks a Digital Logic Verification Engineer to primarily verify FPGA designs, collaborating with cross‑functional teams to deliver robust, high‑quality solutions at our North Reading, MA development center.

The role emphasizes SystemVerilog/UVM test benches, coverage collection, and close interaction with logic designers to ensure design correctness and timely delivery. Experience with CI/CD workflows is a plus.