DFT Lead - Mixed-Signal ASIC Test Architect

Octopyd; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Avicena in Sunnyvale, CA is seeking a DFT Lead to own the test architecture of our mixed-signal ASIC, from scan and BIST through analog test access and production test delivery. You will define the strategy, implement and verify it, and work with product/test engineering to bring it up on the tester.

You will lead DFT engineers, drive coverage targets, collaborate with design on loopback modes, PRBS, memory BIST, and IEEE 1149.1/1687 access, and diagnose silicon issues to reduce test time and

Qualifications

• BS or MS in Electrical or Computer Engineering with 10+ years of DFT experience on production ASICs.
• Hands-on expertise with Siemens Tessent or Synopsys TestMAX/DFTMAX/TetraMAX.
• Scan compression, ATPG, memory BIST and JTAG/IJTAG.
• Gate-level simulation of test patterns and test-mode timing closure.
• ATE bring-up and silicon failure diagnosis.

Responsibilities

• Own the DFT architecture and strategy for a mixed-signal ASIC, including coverage and test-time targets.
• Implement scan insertion and compression, and generate ATPG patterns for stuck-at, transition and path-delay faults.
• Implement memory BIST and repair, and IEEE 1149.1/1687 access for test and instrument control.
• Define link-level test features with the design teams: loopback modes, PRBS generators and checkers, and analog observability and trim access.
• Verify DFT logic and patterns with gate-level simulation, and close test-mode timing with the implementation team.
• Deliver ATE patterns and support tester bring-up with product/test engineering.
• Diagnose silicon failures and support yield learning and test-time reduction.
• Grow DFT capability as the team expands.

Skills

DFT experience

Siemens Tessent

Synopsys TestMAX

DFTMAX

TetraMAX

ATPG

JTAG/IJTAG

gate-level simulation

ATE bring-up

silicon failure diagnosis

Education

BS or MS in Electrical or Computer Engineering

Tools

Siemens Tessent

Synopsys TestMAX

DFTMAX

TetraMAX

Job description

Avicena in Sunnyvale, CA is seeking a DFT Lead to own the test architecture of our mixed-signal ASIC, from scan and BIST through analog test access and production test delivery. You will define the strategy, implement and verify it, and work with product/test engineering to bring it up on the tester.

You will lead DFT engineers, drive coverage targets, collaborate with design on loopback modes, PRBS, memory BIST, and IEEE 1149.1/1687 access, and diagnose silicon issues to reduce test time and