DFT Lead: Innovative Testability Architect (Remote)

BayOne Solutions

United States

Remote

USD 140,000 - 190,000

Full time

3 days ago
Be an early applicant
Application generator

Stand out for this role — generate a tailored resume and cover letter in about a minute.

Get past ATS filters

Job summary

BayOne Solutions seeks a DFT Lead to drive design-for-test features across advanced silicon, coordinating with RTL, test engineers and fabrication teams in a remote, full-time role.

You will implement scan, mbist, boundary scan and BISR, develop DFT IP, and lead post-silicon debug efforts with limited mentorship.

Requires 8–10 years in electrical/computer engineering, strong JTAG, ATPG, and experience with Tessent, Xcelium, Genus and TempPrimetime.

Qualifications

  • Must have 8–10 years of experience in electrical or computer engineering.
  • Proficient with JTAG, scan and BIST architectures including memory BIST and boundary scan.
  • Experience integrating 3rd party IPs and high-speed digital/analog macros.
  • Hands-on post-silicon debugging of DFT patterns (scan/mbist/boundary scan).

Responsibilities

  • Implement Hardware DFT features—scan, mbist, BISR, boundary scan, and DFT simulations debugging.
  • Develop innovative DFT IP and coordinate full chip design integration with RTL testability features.
  • Collaborate with multi-functional teams to drive testability for new silicon device models (bare/stacked dies).
  • Craft solutions and debug with minimal mentorship.

Skills

JTAG protocols
Scan architectures
BIST architectures
Memory BIST
Boundary scan
3rd party IP integration
High-speed macros

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Tessent
Xcelium
Genus
TempPrimetime

Job description

BayOne Solutions seeks a DFT Lead to drive design-for-test features across advanced silicon, coordinating with RTL, test engineers and fabrication teams in a remote, full-time role.

You will implement scan, mbist, boundary scan and BISR, develop DFT IP, and lead post-silicon debug efforts with limited mentorship.

Requires 8–10 years in electrical/computer engineering, strong JTAG, ATPG, and experience with Tessent, Xcelium, Genus and TempPrimetime.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

DFT (Design for Test) Lead
DFT (Design for Test) Lead

BayOne Solutions • United States

Remote
USD 140,000 - 190,000
Lead ASIC/MBIST DFT Engineer - Remote
Lead ASIC/MBIST DFT Engineer - Remote

CAONE • United States

On-site
USD 150,000 - 230,000
ASIC Design-for-Test (DFT)
ASIC Design-for-Test (DFT)

Accord Technologies Inc • San Jose (CA)

On-site
USD 150,000 - 200,000
DFT Engineer (Remote)
DFT Engineer (Remote)

Technical-Link N. America • San Jose (CA)

On-site
USD 120,000 - 180,000
DFT Engineer
DFT Engineer

Akaasa Technologies • Menlo Park (CA)

On-site
USD 103,000 - 165,000
DFT Engineer
DFT Engineer

MatchPoint • San Francisco (CA)

On-site
USD 120,000 - 180,000
DFT Lead
DFT Lead

Eximietas Design • San Francisco (CA)

Hybrid
USD 190,000 - 250,000
Lead ASIC DFT Engineer
Lead ASIC DFT Engineer

ITMC Systems, Inc • San Jose (CA)

On-site
USD 130,000 - 160,000
Lead ASIC DFT engineer.
Lead ASIC DFT engineer.

Accord Technologies Inc • San Jose (CA)

On-site
USD 150,000 - 180,000
DFT Architect
DFT Architect

TYLsemi • United States

Remote
USD 150,000 - 210,000