Lead DFT & ATPG Engineer for SoC/ASIC

AllianceIT Inc; Santa Clara (CA); On-site; USD 130,000 - 170,000; Full time

Job summary

AllianceIT Inc. is seeking a senior DFT/ATPG engineer in Santa Clara, CA to drive test architecture for complex SoC/ASIC designs. You will implement patterns, verify observability, and optimize scan-based strategies across RTL and memory interfaces.

The role requires hands-on experience with MBIST, IO testing, and clock DFT, along with strong problem solving and communication skills. Join a fast-paced semiconductor program and contribute to robust test solutions.

Qualifications

• 5+ years of hands-on experience in DFT and ATPG for SoC/ASIC designs.
• Strong understanding of DFT fundamentals: controllability, observability, and scan testing.
• Proven expertise in ATPG pattern generation, analysis, and debugging.
• Experience with MBIST, memory test architectures and diagnostics.
• Knowledge of IO test methodologies for interface and pin-level validation.
• Solid understanding of clock DFT and clock verification concepts.
• Strong grasp of digital design and RTL fundamentals.
• Experience with industry-standard DFT/ATPG EDA tools.
• Ability to work in fast-paced, high-performance semiconductor programs.
• Strong analytical, problem solving, and communication skills.

Skills

DFT/ATPG experience

DFT fundamentals

ATPG pattern generation

MBIST

IO Test methods

Clock DFT

Digital RTL fundamentals

DFT/ATPG EDA tools

Fast-paced semiconductor

Analytical & communication

Job description

AllianceIT Inc. is seeking a senior DFT/ATPG engineer in Santa Clara, CA to drive test architecture for complex SoC/ASIC designs. You will implement patterns, verify observability, and optimize scan-based strategies across RTL and memory interfaces.

The role requires hands-on experience with MBIST, IO testing, and clock DFT, along with strong problem solving and communication skills. Join a fast-paced semiconductor program and contribute to robust test solutions.