Senior DFT Engineer for SoC/ASIC ATPG & MBIST

Sira Consulting, an Inc 5000 company

California (MO)

On-site

USD 120,000 - 180,000

Full time

23 hours ago
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Job summary

Sira Consulting invites an experienced DFT/ATPG engineer to join our fast-paced semiconductor programs in the United States. You will design and validate test strategies for SoC/ASIC, focusing on controllability, observability, and scan-based testing to ensure high test coverage.

Key responsibilities include ATPG pattern generation, analysis, and debugging, MBIST memory test architectures and diagnostics, and IO test methodologies for interface validation.

Qualifications

  • 5+ years of hands-on experience in DFT and ATPG for SoC/ASIC designs.
  • Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing.
  • Expert in ATPG pattern generation, analysis, and debugging.
  • Experience with MBIST and memory test architectures and diagnostics.
  • Knowledge of IO test methodologies for interface and pin-level validation.
  • Solid understanding of clock DFT and clock verification concepts.
  • Strong digital design and RTL fundamentals.
  • Experience with industry standard DFT/ATPG EDA tools.
  • Ability to work in fast-paced, high-performance semiconductor programs.
  • Strong analytical, problem-solving, and communication skills.

Skills

DFT fundamentals
ATPG (pattern generation)
Scan-based testing
MBIST
Memory test architectures
IO test methodologies
Clock DFT
RTL fundamentals
EDA tools
Problem solving
Communication skills

Tools

DFT/ATPG EDA tools

Job description

Sira Consulting invites an experienced DFT/ATPG engineer to join our fast-paced semiconductor programs in the United States. You will design and validate test strategies for SoC/ASIC, focusing on controllability, observability, and scan-based testing to ensure high test coverage.

Key responsibilities include ATPG pattern generation, analysis, and debugging, MBIST memory test architectures and diagnostics, and IO test methodologies for interface validation.

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