A semiconductor startup in Sunnyvale, CA is seeking a Principal Design Verification Engineer to own the verification strategy and execution for complex IPs or full-chip SoC. This role includes leading a team, establishing plans, and driving collaboration across various engineering teams. The ideal candidate will have 12–15 years of experience in ASIC/SoC design verification, a relevant degree, and expertise in SystemVerilog and UVM methodology. The position offers a compensation range of $250,000–$280,000, along with health coverage and equity options.
Qualifications
12–15 years of experience in ASIC/SoC design verification.
Proven experience leading verification teams and delivering multiple tapeouts.
Strong expertise in functional coverage and assertions.
Responsibilities
Own the verification strategy and execution for complex IPs or full-chip SoC.
Lead development of UVM-based verification environments.
Drive alignment across architecture, RTL, and physical design teams.
Skills
SystemVerilog
UVM methodology
Debugging complex SoC-level issues
Leadership skills
Communication skills
Problem-solving skills
Scripting skills (Python/TCL)
Education
Bachelor’s/Master’s degree in Electrical Engineering or related field
Tools
Synopsys VCS
Cadence Xcelium
Job description
A semiconductor startup in Sunnyvale, CA is seeking a Principal Design Verification Engineer to own the verification strategy and execution for complex IPs or full-chip SoC. This role includes leading a team, establishing plans, and driving collaboration across various engineering teams. The ideal candidate will have 12–15 years of experience in ASIC/SoC design verification, a relevant degree, and expertise in SystemVerilog and UVM methodology. The position offers a compensation range of $250,000–$280,000, along with health coverage and equity options.