Design Verification Engineer

Veracity Ventures Inc.; Santa Clara (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Veracity Ventures Inc. is seeking a Principal Design Verification Engineer in Santa Clara, CA onsite. You will lead verification for multi-core SoCs, architect the verification environment, and guide a team of engineers on projects.

Responsibilities include building reference models, drivers, and monitors, plus developing tools to streamline design verification. Strong C++, ARM assembly, and Linux knowledge are highly desirable.

Qualifications

• BS in Computer Engineering, Electrical Engineering or Computer Science with 10+ years of verification and firmware/software experience (or MS/PhD with 5+ years).
• Proven track record leading Design Verification implementations and tape-out of complex SOC under tight schedules.
• Deep understanding of SystemVerilog and UVM.
• Experience writing detailed test plans and building directed, random verification environments.
• Experience with Python or Perl and EDA verification tools.
• Experience with Object-Oriented Design and implementation.
• Good Linux OS knowledge; strong C++ and ARM assembly programming skills.
• Understanding of networking protocols is a plus.

Responsibilities

• Write a verification test plan using random techniques and work with designers to ensure completeness.
• Develop tests and tune the environment to achieve coverage goals; debug failures with designers.
• Verify boot code and architect, develop, and maintain tools for scalable SOC design.
• Translate engineering requirements into user-friendly, scalable software tools for parallel compute environments.
• Perform unit and regression testing of software tools.

Skills

SystemVerilog

UVM

Python

Perl

C++

ARM assembly

Object-Oriented Design

Linux

Education

BS in Computer Engineering / Electrical Engineering / Computer Science

MS/PhD with 5+ years experience

Tools

SystemVerilog

UVM

EDA Verification tools

Job description

Design Verification Engineer, Principal

Santa Clara, CA - Onsite

Full Time

As a leading member of the Network Switching team you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development. Your role may also include project management and leading a team of verification engineers on a project level.

Activities may include:

• Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.


• Developing tests and tuning the environment to achieve coverage goals. Debugging failures and working with designers to resolve issues.


• Verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs.


• Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment.


• Unit and regression testing of software tools.

What We're Looking For

• BS Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware and software development experience (or MS/PhD with 5+ years experience).


• Proven track records of leading Design Verification implementation activity. Tape-out of complex SOC under tight schedule.


• In depth understanding and experience with System Verilog, UVM.


• In depth experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment.


• Experience with scripting language such as Python or Perl and EDA Verification tools.


• Experience with Object-Oriented Design and implementation.


• Good understanding of Linux O.S.


• Good programming skills desired, especially C++ and ARM assembly.


• Understanding of networking protocols, a plus.