Lead Design Engineer — RTL, Timing & Tapeout

Cadence Design Systems; Cary (NC); On-site; USD 120,000 - 180,000; Full time

Job summary

Cadence Design Systems in Cary, NC seeks an experienced IC design engineer to lead timing closure and tape-out activities for Palladium and Protium SOCs. You will contribute to RTL synthesis, floorplanning, clock-tree construction, and physical verification, collaborating with Front End RTL and Back End Verification teams.

The role requires 5+ years of E/E experience or 3+ years with MS, proficiency with Cadence tools (Innovus, Tempus, QRC, Voltus, Pegasus), and familiarity with 5nm/3nm/2nm

Qualifications

• BS degree in Electrical Engineering with 5+ years of experience or MS with 3+ years.

Responsibilities

• Implement, verify, timing closure to tape out Palladium and Protium SOCs.
• Work on RTL synthesis and floorplanning.
• Build clock trees and perform optimizations.
• Close timing, IR drop and physical verification.
• Review and document designs for taping out.
• Interface with Front End RTL design teams and Back End Verification teams.

Skills

Electrical engineering

Scripting (Shell/Perl/TCL/Python)

Linux experience

PCIe/DDR/UCIe knowledge

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Innovus

Tempus

QRC

Voltus

Pegasus

Job description

Cadence Design Systems in Cary, NC seeks an experienced IC design engineer to lead timing closure and tape-out activities for Palladium and Protium SOCs. You will contribute to RTL synthesis, floorplanning, clock-tree construction, and physical verification, collaborating with Front End RTL and Back End Verification teams.

The role requires 5+ years of E/E experience or 3+ years with MS, proficiency with Cadence tools (Innovus, Tempus, QRC, Voltus, Pegasus), and familiarity with 5nm/3nm/2nm