Lead Design Engineer

Cadence; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

Cadence is seeking a Digital Design Engineer to design and integrate IPs into SoCs based on customer specifications. You will perform Lint/CDC checks, create synthesis constraints, and support verification and physical design teams. The role emphasizes automation and cross-team collaboration.

Qualifications include 5–8 years in digital design, strong Verilog/SystemVerilog, and experience with AMBA protocols and high-speed IPs like PCIe, Ethernet, and DDR.

Qualifications

• Bachelor level degree in electronics/EE; 5–8 years in digital design.
• Experience with Verilog/SystemVerilog and AMBA protocols is preferred.

Responsibilities

• Design and integration of IPs in SoC from customer specs.
• Perform Lint/CDC checks for quality and fix issues.
• Create synthesis constraints and basic synthesis for PPA optimization.
• Create microarchitectural specification documents.
• Support verification: test plans, coverage, debugging.
• Support physical design team as needed.
• Automate repetitive tasks and drive efficiency.
• Collaborate across teams for project success.

Skills

Digital design fundamentals

Verilog/SystemVerilog

Scripting (Python/Perl/Tcl)

Automation of repetitive tasks

Cross-functional collaboration

AMBA protocols

PCIe/Ethernet/DDR IPs

STA (Static Timing Analysis)

Synthesis constraints

Education

B.E./B.Tech/M.Tech in Electronics/EE

Tools

Lint/CDC tools

Xcelium

Verisium

Synthesis tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities:

• Design and integration of IPs in SoC based on high-level architectural specifications from customers.
• Perform Lint/CDC checks on the design for quality assurance and resolve related issues.
• Create synthesis constraints for the design at the IP and SoC level and perform basic synthesis for PPA (Power, Performance, Area) optimization.
• Create detailed Microarchitectural Specification documents for the design.
• Provide support to the verification team for test plan creation, coverage analysis, and feature debugging.
• Provide support to the physical design team as needed for design implementation.
• Implement innovative solutions to automate repetitive tasks.
• Collaborate within and across teams for effective project execution.

Requirements:

• B.E./B.Tech/M.Tech with 5-8 years of experience as a digital design engineer.
• Strong knowledge of digital design fundamentals and Verilog/SystemVerilog (SV).
• Solid knowledge of Lint/CDC tools and the ability to set up flows from scratch.
• Knowledge of creating synthesis constraints and Static Timing Analysis (STA); familiarity with synthesis tools is a plus.
• Familiarity with simulation tools (e.g., Xcelium, Verisium) to support verification.
• Experience with AMBA protocols and other ARM IPs is a plus.
• Experience with high-speed IPs such as PCIe, Ethernet, and DDR is a plus.
• Proficiency in scripting languages (Python/Perl/Tcl).
• Ability to innovate and automate repetitive tasks.
• Good communication skills for effective cross-functional collaboration.

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