Lead Design engineer

Cadence; Shanghai (VA); On-site; USD 120,000 - 160,000; Full time

Job summary

Cadence is seeking a candidate to collaborate with design and verification teams to guarantee thorough test coverage and robust verification practices for seamless project execution.

The role also bridges communication between local teams and global stakeholders, with hands-on experience in AMBA, PCIe, USB, MIPI or DDR/LPDDR, and preferred ARM/RISC-V processor integration. This position emphasizes leadership and collaboration across sites.

Qualifications

• Experience in hardware verification and test coverage.
• Strong collaboration and communication skills in cross-site teams.
• Familiarity with industry protocols such as AMBA, PCIe, USB, MIPI or DDR/LPDDR.

Responsibilities

• Collaborate closely with design and verification teams to ensure comprehensive test coverage and robust verification methodology.
• Bridge communication between local teams and global stakeholders to enable seamless project execution.

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The ideal candidate will collaborate closely with design and verification teams to ensure comprehensive test coverage, robust verification methodology, and seamless project execution. Will play a key role in bridging communication between local teams and global stakeholders. Hands-on experience in any protocol like AMBA, PCIe, USB, MIPI or DDR/LPDDR. ARM/RISC-V Processor integration experience preferred.

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