Principal Design Engineer

Cadence Design Systems; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Cadence Design Systems is seeking an experienced digital design engineer to design and integrate IPs for complex SoCs. You will use Verilog/SystemVerilog, run Lint/CDC checks, and create synthesis constraints for PPA optimization.

You will support verification and physical teams, automate repetitive tasks, and collaborate across multiple disciplines to deliver high-quality designs. Applicants should have 8–12 years of hands-on digital design experience, AMBA/ARM IP familiarity, and strong

Qualifications

• B.E./B.Tech./M.Tech in Electrical Engineering is required.
• 8–12 years of experience as a digital design engineer.
• Strong knowledge of digital design fundamentals and Verilog/SystemVerilog (SV).
• Experience with Lint/CDC tools and setting up flows from scratch.

Responsibilities

• Design and integration of IPs in SoC based on high-level architectural specifications from customers.
• Perform Lint/CDC checks on the design for quality assurance and resolve related issues.
• Create synthesis constraints for the design at the IP and SoC level and perform basic synthesis for PPA optimization.
• Create detailed Microarchitectural Specification documents for the design.
• Provide support to the verification team for test plan creation, coverage analysis, and feature debugging.
• Provide support to the physical design team as needed for design implementation.
• Implement innovative solutions to automate repetitive tasks.
• Collaborate within and across teams for effective project execution.

Skills

Digital design

Verilog/SystemVerilog

Lint/CDC flows

Synthesis constraints

STA timing analysis

AMBA protocols

PCIe/Ethernet/DDR

Python/Perl/Tcl

Strong communication

Education

B.E./B.Tech./M.Tech in Electrical Engineering

Tools

Xcelium

Verisium

Synthesis tools

Job description

Responsibilities

• Design and integration of IPs in SoC based on high-level architectural specifications from customers.
• Perform Lint/CDC checks on the design for quality assurance and resolve related issues.
• Create synthesis constraints for the design at the IP and SoC level and perform basic synthesis for PPA (Power, Performance, Area) optimization.
• Create detailed Microarchitectural Specification documents for the design.
• Provide support to the verification team for test plan creation, coverage analysis, and feature debugging.
• Provide support to the physical design team as needed for design implementation.
• Implement innovative solutions to automate repetitive tasks.
• Collaborate within and across teams for effective project execution.

Requirements

• B.E./B.Tech/M.Tech with at least 8-12 years of experience as a digital design engineer.
• Strong knowledge of digital design fundamentals and Verilog/SystemVerilog (SV).
• Solid knowledge of Lint/CDC tools and the ability to set up flows from scratch.
• Knowledge of creating synthesis constraints and Static Timing Analysis (STA); familiarity with synthesis tools is a plus.
• Familiarity with simulation tools (e.g., Xcelium, Verisium) to support verification.
• Experience with AMBA protocols and other ARM IPs is a plus.
• Experience with high-speed IPs such as PCIe, Ethernet, and DDR is a plus.
• Proficiency in scripting languages (Python/Perl/Tcl).
• Ability to innovate and automate repetitive tasks.
• Good communication skills for effective cross-functional collaboration.

Equal Employment Opportunity Policy

Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact [e-mail]. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab).

E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K)

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer.

All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.