Lead SoC Design Architect & Automation Innovator

Cadence; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

Cadence is seeking a Digital Design Engineer to design and integrate IPs into SoCs based on customer specifications. You will perform Lint/CDC checks, create synthesis constraints, and support verification and physical design teams. The role emphasizes automation and cross-team collaboration.

Qualifications include 5–8 years in digital design, strong Verilog/SystemVerilog, and experience with AMBA protocols and high-speed IPs like PCIe, Ethernet, and DDR.

Qualifications

• Bachelor level degree in electronics/EE; 5–8 years in digital design.
• Experience with Verilog/SystemVerilog and AMBA protocols is preferred.

Responsibilities

• Design and integration of IPs in SoC from customer specs.
• Perform Lint/CDC checks for quality and fix issues.
• Create synthesis constraints and basic synthesis for PPA optimization.
• Create microarchitectural specification documents.
• Support verification: test plans, coverage, debugging.
• Support physical design team as needed.
• Automate repetitive tasks and drive efficiency.
• Collaborate across teams for project success.

Skills

Digital design fundamentals

Verilog/SystemVerilog

Scripting (Python/Perl/Tcl)

Automation of repetitive tasks

Cross-functional collaboration

AMBA protocols

PCIe/Ethernet/DDR IPs

STA (Static Timing Analysis)

Synthesis constraints

Education

B.E./B.Tech/M.Tech in Electronics/EE

Tools

Lint/CDC tools

Xcelium

Verisium

Synthesis tools

Job description

Cadence is seeking a Digital Design Engineer to design and integrate IPs into SoCs based on customer specifications. You will perform Lint/CDC checks, create synthesis constraints, and support verification and physical design teams. The role emphasizes automation and cross-team collaboration.

Qualifications include 5–8 years in digital design, strong Verilog/SystemVerilog, and experience with AMBA protocols and high-speed IPs like PCIe, Ethernet, and DDR.